0.36mW, 52Mbps True Random Number Generator Based on a Stochastic Delta-Sigma Modulator

A true random number generator (TRNG) is suitable for generating secure keys and nonces. TRNGs implemented in IoT devices must be small in scale and have low power consumption. The random number sequence generated by TRNG needs to have high entropy immediately after startup and a stable state. In this paper, three types of ring oscillator type TRNGs, TERO-based, COSO-based, and STR-based TRNG, are implemented on Zynq-7010. When these TRNGs are implemented as a single entropy source, it is challenging to implement them because it is necessary to evaluate the layout and wiring for each FPGA. This paper proposes a TRNG configuration, which exclusively ORs the outputs of multiple entropy sources. We show that this configuration can reduce the implementing difficulty and realize high entropy. For the random number sequence evaluation, we use the statistical test of NIST SP800-90B and BSI AIS 20/31. In addition, the random number sequence immediately after the startup is also statistically evaluated. As a result, our proposed TRNGs generate high entropy random numbers and are easy to implement on FPGA when we implement TRNGs with eight single entropy sources for TERO-based TRNG, 48 for COSO-based TRNG, and two for STR-based TRNG, respectively.

True random number generators (TRNG) are widely used to generate encryption keys in information security systems [1]–[2]. In TRNG, entropy source is a critical module who provides the source of randomness of output bit stream. The unavoidable electrical noise in circuit becomes an ideal entropy source due to its unpredictability. Among the methods of capturing electrical noise, ring oscillator-based entropy source makes the TRNG most robust to deterministic noise and 1/f noise which means the strongest anti-interference capability, so it is simple in structure and easy to integrate [3]. Thus, great research attention has focused on ring oscillator-based TRNGs [3] –[7]. In [4], a high-speed TRNG with 100Mbps output bit rate was proposed, but it took up too much power and area. A TRNG based on tetrahedral ring oscillator was proposed in [5]. Its power consumption was very low but the output bit rate was also very low. A ring oscillator-based TRNG with low output bit rate but high power was proposed in [7]. In a word, none of the above architectures achieve an appropriate compromise between bit rate and power consumption. This work presents a new feedback architecture of TRNG based on tetrahedral ring oscillator. The output random bit stream generates a relative random control voltage that acts on the transmission gates in oscillator through a feedback loop, thus increasing phase jitter of the oscillator and improving output bit rate. Furthermore, an XOR chain-based post-processing unit is added to eliminate the statistical deviations and correlations between raw bits.

A demultiplexer-based dual-path switching true random number generator

The generation of random numbers is crucial for practical implementations of cryptographic algorithms. In this sense, hardware security modules (HSMs) include true random number generators (TRNGs) implemented in hardware to achieve good random number generation. In the case of cryptographic algorithms implemented on FPGAs, the hardware implementation of RNGs is limited to the programmable cells in the device. Among the different proposals to obtain sources of entropy and process them to implement TRNGs, those based in ring oscillators (ROs), operating in parallel and combined with XOR gates, present good statistical properties at the cost of high area requirements. In this paper, these TRNGs are revisited, showing a method for area optimization independently of the FPGA technology used. Experimental results show that three ring oscillators requiring only three LUTs are enough to build a TRNG on Artix 7 devices from Xilinx with a throughput of 33.3 Kbps, which passes NIST tests. A throughput of 50 Kbps can be achieved with four ring oscillators, also requiring three LUTs in Artix 7 devices, while 100 Kbps can be achieved using an structure with four ring oscillators requiring seven LUTs.

The transition effect ring oscillator (TERO) based true random number generator (TRNG) was proposed by Varchola and Drutarovsky in 2010. There were several stochastic models for this advanced TRNG based on ring oscillator. This paper proposed an improved TERO based TRNG and implements both on Altera Cyclone series FPGA platform and on a 0.13um CMOS ASIC process. FPGA experimental results show that this balanced TERO TRNG is in good performance as the experimental data results past the national institute of standards and technology (NIST) test in 1M bit/s. The TRNG is feasible for a security SoC.

A reconfigurable PUF structure with dual working modes based on entropy separation model

Physical Unclonable Functions (PUFs) and True Random Number Generators (TRNGs) are common primitives that can increase the security of user logic on FPGAs. They are typically constructed using Ring Oscillators (ROs). However, PUF and TRNG primitives are not currently available on Cloud FPGAs as some commercial Cloud FPGA providers prohibit deploying ROs implemented using Lookup Tables (LUTs). To aid in bringing RO-based PUFs and TRNGs to commercial Cloud FPGAs, this work implements and evaluates PUFs and TRNGs built using ROs that incorporate latches and flip-flops. The primitives are tested on Amazon's commercial F1 Cloud FPGAs. The designs are the first constructive uses of ROs in Cloud FPGAs and are available under an open-source license.

Many side channels including power consumption, electromagnetic emanation, optical radiation, and even sound have been studied since the first publication of a side channel attack at the end of the 1990s. Most of these channels can be relatively easily used for an overall analysis of the cryptographic system (implementation of efficient passive attacks) or for injection of faults. Until recently, only the optical channel allowed both analysis of locally leaked information and precise injection of faults (single-bit errors). Recent works showed that the near-field electromagnetic channel enables similar results to be obtained. Like the optical channel, the near-field electromagnetic channel allows both active and passive attacks, which, in addition, can be theoretically non-invasive and contactless. However, the cost of the attack bench that is needed to exploit the near-field electromagnetic channel is less than that of an optical channel. Recently, we showed that it is possible to use the near-field electromagnetic channel to perform an efficient active attack targeting the true random number generator (TRNG) based on ring oscillators. In cryptography, TRNGs are chiefly used to generate encryption keys and other critical security parameters, so the proposed active attack could have serious consequences for the security of the whole cryptographic system. Here, we present the coupling of a passive attack and an active attack. The proposed coupled attack first uses a spectral differential analysis of the TRNG electromagnetic radiation to obtain valuable information on the position of ring oscillators and their frequency range. This information is then used to tune the electromagnetic harmonic signal to temporarily synchronize the ring oscillators. In this paper, we propose a fault model of the entropy extractor which shows that the behavior of the ring oscillators changes, and that it occurs additional and unwanted “fake rising edges” of the clock signal which disturb the flip-flops involved in such TRNGs. The effectiveness of our proposed coupled attack questions the use of ring oscillators in the design of TRNGs.

In this work, we present a chaos based integrated jitter booster circuit for use in multiple oscillator sampling true random number generator architecture. Multiple ring oscillator based true random number generators need significant number of rings for accumulating the intrinsic jitter of inverters to a useful level. Thus, they occupy large silicon area and consume considerable amount of power. The proposed circuit offers an alternative approach for boosting jitter using the chaotic dynamics generated by non-linear coupling of two ring oscillators that require fewer number of components. The simplicity of the proposed circuit offers high integration potential with inherent low area and power consumption advantages. Chaotic dynamics of the circuit was studied using both numerical and circuit simulations. Measurement results of the test chip implemented at 250nm CMOS technology node confirmed chaotic behavior and jitter boosting capability. To the very best of our knowledge this is the first integrated circuit implementation of a chaotic circuit based on digital gates.

True random number generators (TRNGs) based on ring oscillators (ROs) are employed in many devices because they can be constructed with a simple circuit structure. Many systems are affected if an RO-based TRNG is attacked, and its security is degraded. Conventional attacks against RO-based TRNGs reduce randomness using direct physical access to the target device and/or modification/invasion of the device or the equipment on which it is implemented. However, depending on the physical location of the device and its tamper resistance measures, directly accessing the device or operating/modifying the implementation may not be easy. This study introduces a noninvasive attack against RO-based TRNGs. In this attack, we intentionally induce sinusoidal electromagnetic waves in a TRNG and estimate the change in its randomness under this interference by observing the signal leaked from the TRNG from a distance. We also consider countermeasures against noninvasive attacks on TRNGs.

True random number generator (TRNG), plays an important role in information security systems. Conventional TRNGs use natural physical stochastic processes including thermal noise, chaos-based circuit and so on to generate the random numbers. These analog circuit based TRNG structures often consume lots of hardware resources, and are not easy to be integrated in digital systems. In this paper, a low-cost and high-speed TRNG has been proposed by using mixed oscillation generated from XOR gates nested multiple ring oscillators (ROs). Multi-group mixed oscillation XOR operation is applied to obtain high-speed output. The proposed TRNG design is implemented on Xilinx Artix-7 XC7A35T-1FTG256C FPGA. It achieves a high performance with throughput up to 160 Mbps and with a usage of 37 FFs and 25 look up tables (LUTs) in the FPGA. The results show that the proposed TRNG design has successfully passed the testing standards of NIST SP800-22 and AIS31. Compared with previous designs, the proposed TRNG design achieves lower hardware resource consumption and higher speed.

Random numbers are at the heart of diverse fields, ranging from simulations of stochastic processes to classical and quantum cryptography. The requirement for true randomness in these applications has motivated various proposals for generating random numbers based on the inherent randomness of quantum systems. The generation of true random numbers with arbitrarily defined probability distributions is highly desirable for applications, but it is very challenging. Here we show that single-photon quantum walks can generate multi-bit random numbers with on-demand probability distributions, when the required “coin” parameters are found with the gradient descent (GD) algorithm. Our theoretical and experimental results exhibit high fidelity for various selected distributions. This GD-enhanced single-photon system provides a convenient way for building flexible and reliable quantum random number generators. Multi-bit random numbers are a necessary resource for high-dimensional quantum key distribution.

In this paper, we propose a Ferroelectric Tunnel Junction (FTJ)-based true random number generator (TRNG) that utilizes the stochastic domain switching phenomenon in ferroelectric materials. Ferroelectrics are promising for extracting randomness owing to their innate switching entropy in the multi-domain state. The random numbers generated by the proposed TRNG are shown to pass all the NIST SP 800-22 tests. The robustness of the proposed TRNG is also validated at various temperature and process corners. Important metrics such as power, bit rate, and energy/bit are calculated. This is the first comprehensive work demonstrating a ferroelectric-based TRNG with all these metrics. Compared to state-of-the-art TRNGs using other emerging technologies, we can achieve a higher bit rate with lower power consumption. We also perform material-level optimization with different ferroelectric materials, and showcase the trade-off between the bit rate and the power consumption. The proposed TRNG shows high robustness and reliability, and thus has the potential for implementing a low power on-chip solution.

We design a cryptographic transistor (cryptoristor)-based true random number generator (tRNG) with low power consumption and small footprint. This is the first attempt to use irregular and unpredictable operation-induced randomness of a cryptoristor as an entropy source. To extract discrete random numbers with a binary code from the cryptoristor, we developed a noise-coupling analog-to-digital converter. This converter not only converts analog signals to digital random bits but also improves the randomness of the entropy source with low power consumption. The randomness of the cryptoristor is attributed to the random carrier multiplications with the creation and stochastic carrier escape as destruction, which occurs iteratively as long as the input current is fed. The cryptoristor-based tRNG passed 15 randomness test suites of NIST Special Publication 800-22. It is robust to iterative operational stresses and to ambient temperature changes, making it an attractive option for hardware-based security solutions in the Internet of Things due to its low power consumption and small size.

Printed electronics (PE) is a fast-growing field with promising applications in wearables, smart sensors, and smart cards, since it provides mechanical flexibility, and low-cost, on-demand, and customizable fabrication. To secure the operation of these applications, true random number generators (TRNGs) are required to generate unpredictable bits for cryptographic functions and padding. However, since the additive fabrication process of the PE circuits results in high intrinsic variations due to the random dispersion of the printed inks on the substrate, constructing a printed TRNG is challenging. In this article, we exploit the additive customizable fabrication feature of inkjet printing to design a TRNG based on electrolyte-gated field-effect transistors (EGFETs). We also propose a printed resistor tuning flow for the TRNG circuit to mitigate the overall process variation of the TRNG so that the generated bits are mostly based on the random noise in the circuit, providing a true random behavior. The simulation results show that the overall process variation of the TRNGs is mitigated by 110 times, and the generated bitstream of the tuned TRNGs passes the National Institute of Standards and Technology - Statistical Test Suite. For the proof of concept, the proposed TRNG circuit was fabricated and tuned. The characterization results of the tuned TRNGs prove that the TRNGs generate random bitstreams at the supply voltage of down to 0.5 V. Hence, the proposed TRNG design is suitable to secure low-power applications in this domain.