0.4 mm PoP Assembly Development and Reliability

PoP, Package-on-Package, becomes more and more popular in IC packaging industry because it provides a practical solution to reduce the footprint and enables separate package test before stacking them. It is widely accepted at mobile devices, especially for logic (bottom) plus memory (top) application. Meanwhile there are several technical challenges such as top to bottom package connection problem caused by warpage, fine pitch package stack issue due to bottom package mold height and worse thermal performance than that of a single stacked package. While many studies have been conducted on warpage and new type PoP for fine pitch interconnection, there is few existing study on the thermal performance of PoP. This paper investigates thermal characteristic of PoP, especially on the thermal interactions between bottom and top packages. CFD models are established to study such interactions. It is found that bottom package usually with a higher power logic die inside has great impact on the thermal budget of top package, which is usually a stacked memory package. Normal JEDEC junction to air (thetasja) or junction to board (thetasjb) thermal resistance cannot clearly describe the PoP thermal performance since the heat distribution between top and bottom package will greatly affect the results. A thermal resistance network is proposed to better represent the performance and can also give a quick estimation of junction temperature for simple calculation. The present paper then uses some fixed power of bottom and top package to evaluate different options of improving the thermal performance.

The continued demand for higher level of integration has led to the industry's adoption of 3D packaging technologies and, in particular, the Package-On-Package (PoP) configurations. This technology allows for vertical integration of the memory package and the logic package into one stacked package. The top package is primarily a memory module including some combination of Flash and SDRAM, while the bottom package typically contains the logic die, which is a baseband or an application processor of some kind. Top and bottom package are connected via the pads that are located on the top side of the bottom PoP package, and these pads are used to connect the top PoP (memory module) Ball Grid Array (BGA) solder balls to the bottom PoP package. This paper details the various PoP package types including bare-die PoP, Embedded Solder On Pad (eSOP) PoP, and Laser-Via PoP that have proliferated to meet the increasing market demand. Also, the various package types are compared to each other in terms of their feasibility for adoption in the next generation PoP with tighter pitch and lower package profile.

As mobile and other electronic devices become smaller with more sophisticated functions the assembly technologies for compact and high-density packages have advanced dramatically. Recently Package on Package (PoP) technology has increased in use in the industry. In the conventional PoP manufacturing process, the solder bumps of the top package are immersed into a layer of tacky flux. Once the flux immersion is completed, the top package is placed on to the bottom package and soldered together. One of the challenges of PoP manufacturing is component warpage during the reflow process which had led to the incomplete merger of the solder bump from the top package with the solder land on the bottom package. Once the solder bumps of the top PoP component separate from the land of the bottom component, even if they come into contact again, the tacky flux activity is reduced leading to incomplete merger. The work focused on the development of solder paste rather than tacky flux for PoP manufacturing to reduce the incomplete merger occurring during soldering. The solder paste would have the benefit of reducing the gap between the land and solder bumps caused by component warpage, and would hold the two together more when molten to prevent incomplete merger. Tests were conducted on lead-free PoP solder pastes with adjustments in the flux thixotropic agents, activators and solvents in addition to the actual flux content used in the solder paste. The results of the investigations are presented.

Due to rapid growth in the mobile industry, Package-on-Package (PoP) has been widely adopted for 3D integration of logic and memory devices within mobile handsets, and other portable multimedia products, etc. Typical PoP configuration includes a logic function in the bottom package while memory dice are assembled into the top package. The TMV solution is widely adopted to reduce package warpage, to achieve a fine pitch PoP, and to stabilize stacking performance. Another big benefit of the TMV is to generate a thin structure by exposing the back side of the die using a film assist mold system. However, the trend of mobile devices is going thinner and thinner, and there is a limitation to achieve the thin PoP structure. The most difficult barrier to generate the thin PoP structure is the warpage control. In this paper, a strip grinding process is introduced as a solution to generate thinner PoP structures in overmolded packages. Applying the strip grinding process to exposed die, reducing mold clearance, and exploring double sided mold structures to reduce die/package height were also investigated.

The recent requirements for achieving higher memory density in a smaller package size have adopted 3D packaging of thin dies in a single package. However, increasing the number of dies in 3D stacking is limited by increasing the cost due to decrease die stacking yield. The known good package stacking can be solution to overcome such yield loss. In this study, a novel Fan-in PoP solution proposed, stacking two package which have stacked multiple dies each and interconnecting the package through blind EMC via without changing package size. The solder ball of top package fills up the blind EMC via during the reflow process. In order to evaluate the board level reliability, Fan-in PoP(QDP-DSP : Quad Die Package - Dual Stack Package) was mounted to a FR-4 board. Fan-in PoP with various solder compositions wes explored regarding the failure mode, crack propagation and life time under the drop test and thermal cycling test compared to those of ODP (Octa Die Package). The Fan-in PoP showed superior drop performance compared to ODP due to the package flexibility. On the other hand, thennal cycling test results showed a little increased life time compared to ODP. The solder joint formation on the silicon chip through blind EMC via causes the serious thermal stress concentration due to the silicon stiffness.

In the last half a century, the complexity of electronic systems has undergone a sustainable rapid development stage following the Moore's law: the density of integrated circuits (ICs) was doubled every two years. As a result, electronic devices become more miniaturized in space and contain more power in unit volume. Electronic package has to deal with highly increased I/Os with fine soldering pitch. A symbol of the fast development of the package technology is using staked technique to develop three-dimensional (3D) package from 2D and 2.5D. The representative products are the package-on-package (PoP) technology in which packages are staked and through-silicon-via (TSV) technology in which chips are staked. The PoP has been widely used in handheld products such as cell phones and PDA. The harsh environment in service and high integration in composition have brought big challengers to the design and process of the package. PoP technology has attracted great attentions. The staked composition has largely reduced the length of connection lines between packages. It is also coupled with modules design concept in which different functions can be contained in different packages and thus results in a convenience for efficient production. In view of the advantages, PoP is favored by cell phones and other handheld products. A great deal of work has been done on the general issues. However, given the short life period, detailed studies on specific aspects and individual products have not been covered in full. These include such aspects as the effects of pad design, stencil design and soldering profile on the reliability of PoP systems. The issue for how to increase the pass rate of soldering satisfactory under extreme deformations has also not been seen by the authors in report. PoP has raised challengers to package design. As a staked system, interactions are intensified between packages: the deformation due to the difference of the coefficient of thermal expansions (CTE) will be accumulated and the heat cannot be dispersed through the surfaces between packages. Furthermore, the staked packages become difficult to bend following the PCB as performed by single thin package. All the above factors can deteriorate mechanical damage. So we will work on investigation of the manufacturability and reliability of a PoP system through an integration of modeling, testing and design modification. This includes (i) finite element analysis (FEA) of the PoP system to identify the critical regions and deformation; (ii) experimental test of the PoP system to validate the FEA results; (iii) evaluation of the impact of thermal deformation on the quality and reliability of solder joints to form guidance for detail designs of PoP systems. Agreed results have been achieved from our modeling and testing. The thermal damage to the PoP system has been realized. The effect of manufacturing details of pad, stencil and soldering on the reliability of PoP systems has been analyzed. A guide for design procedure has been offered. Through this integrated investigation, we have obtained a good understanding to the mechanical performance of PoP systems and found the way for how to design relevant details for enhanced reliability. This has practical reference to PoP design and testing. In this paper, we work on the parts of integration modeling: research on printed board's deformation. Finite element method is used to predict the deformation of printed board in different copper case, testing the PCB s deformation by use moire, and correcting finite element model, after we master PCB deformation, we could design PCB such as layout, routing, and wiring to pave the way for the production of POP. Subsequent work with experimental continue to be in a future paper published in succession.

The needs to integrate devices into portable products with smaller form factor and more functionality have fueled enormous growth of 3D packaging technology. The package-on-package (PoP) is one of the 3D packaging solutions, by which the packaging and assembly houses can achieve a lower cost, faster turn benefits and testing prior to assembly. PoP is a complicated system with multi-layered structure, which induces more manufacturability issues, such as stand-off height issue and top & bottom packages having different types of warpage. In order to reduce R&D cost, achieve fast time-to-market and address most of the manufacturability issues during the development of a new PoP, a design advisor for PoP manufacturing has been developed based on the design for manufacturability (DFM) methodology. The key components of this design advisor are the validated numerical models, comprehensive materials library, design guidelines of PoP packaging and novel finite element analysis (FEA) techniques. With the developed novel FEA techniques for curing process simulation and seamless packaging process simulation, complete numerical models for PoP manufacturing were developed and validated, which can simulate the whole PoP manufacturing processes. The design advisor is easy to use by selecting package geometries, material properties and process parameters. By running the envelope-based design advisor for normal package design or the FEA-based design advisor for special package design, the detailed analysis reports can be generated, including simulation results, design evaluations and recommendations to ensure the first-time success of package design. Therefore, the design advisor can help improve the yield of complex PoP manufacturing processes leading to higher quality and confidence of manufacturing processes, faster time-to-market and lower overall manufacturing cost.

The IC (integrated circuit) packaging technology has evolved and transitioned from wirebond to flipchip, multi-chip package (MCP) to 3D stacking. PoP (Package on Package) enables the vertical integration of memory on the conventional package which helps to achieve higher component density on the platform. PoP technology is very important for modern electronics devices as it features more function in very compact devices such as smart phones and tablets. While PoP offers denser component count on platform, it also comes with electrical challenges such as Power Integrity issue. Conventional Power Integrity Design and Methodology may not hold for PoP technology.

In the embedded wafer-level packaging field, the embedded micro wafer level package (EMWLP) technology leverages on fan-out redistribution connections, keeping the reliance on wire-bonding and flip-chip bump connections to a minimum, thus streamlining the packaging process. As the embedded micro wafer level packaging (EMWLP) technology evolves to capitalize on package-on-package (POP) technology, this study's parametric thermal modeling focuses on analyzing the thermal impact of increased density in a low thermal conductivity packaging material. The package design in this work has the following specifications: the memory EMWLP (die size: 7×7×0.2mm) on logic EMWLP structure (die size : 8×8×0.2mm), sized 12×12×0.9mm in total. The POP structure, furthermore, incorporates through-mold-interconnects (TMI) in the bottom logic package to provide short electrical connection from the top package to the board level. The impact on multi-package thermal resistance is then studied as the following parameters vary: power dissipation (in both packages); mold conductivity; number of TMIs; number of solder ball connections; inclusion and size of an interpackage heatslug; inclusion and thermal conductivity of a top heatspreader. The thermal management of the dies are also studied based on the above measures and was found to accommodate under 4W of total POP power. Finally, simulation results for a general system-level thermal modeling of the EMWLP POP in a cellphone scenario are also conducted with passive thermal management solutions proposed.

Fan-out wafer level packaging (FOWLP) is one of the latest technologies to meet the requirements of high performance and thin form-factor, especially for mobile application processors. To achieve a simple path way and thinner package form, many outsourced semiconductor assembly and test (OSAT) suppliers and foundries provide FOWLP capabilities. Most solutions are limited to the bottom 2D package area with a package on package (PoP) stacking structure to communicate logic to memory or a peripheral chip beyond the 2D distribution area. This means that communication between heterogeneous chips has more power and signal loss by PoP interconnection to reach hetero-chip functions through bulk solder ball joints and printed circuit board (PCB) laminated routing with more coarse trace pattern than a fan-out (FO) redistribution layer (RDL pattern). To improve this situation, high performance heterogeneous integration has been simulated and successfully realized with the novel 3D Silicon Wafer Integrated Fan-out Technology (SWIFT®) prototype as chip stackable, ultra-thin, high flexibility FOWLP for the first ultimate 3D packaging. Also, this has been proven to be a highly flexible and cost-effective structure with a low-risk process flow, low package warpage, stable electrical performance, and good reliability performance. The form-factor of the 3D SWIFT design with various structure options is as much as 45% thinner than PoP technology.

As the demands of higher performance, higher bandwidth, lower power consumption as well as multiple functions increases in mobile applications, the mobile phone has evolved from a simple communication device to a complicated and highly integrated system with multiple functions and heterogeneous devices. Due to the fast growth in emerging markets for mobile applications, packaging technology has become more challenging than ever before, driving advanced Silicon (Si) nodes, finer bump pitch as well as finer line width and spacing substrate manufacturing capabilities to satisfy the increasing requirements in mobile devices. Flip chip chip scale package (fcCSP) is viewed as an attractive solution when higher input/output (I/O) counts in a package are needed. In order to enhance the performance, reduce the power consumption and increase transition rates, three-dimensional (3D) package-on-package solution with flip chip interconnect (fcPoP) has been widely utilized to successfully achieve these goals. With the ability to stack a logic processor and low power double data rate (LPDDR) memory device in a single package, the utilization of fcPoP is becoming a preferred solution in the mobile market segment for a better power and performance balance. However, as more and more functions are designed in a chip to target the high-end mobile market, the die is becoming larger and larger. With the larger die size, it is challenging for the regular fcPoP structure to support high bandwidth top memory I/O counts in a limited package size. In order to solve the constraints of larger die and/or package size limitations, top memory with wide I/O counts as well as customized mobile memory applications, high bandwidth fcPoP technology is proposed as an strong solution. This paper reports the development of a fine pitch high bandwidth fcPoP. The top interposer substrate with copper (Cu) post interconnections peripherally is connected to bottom package. The top interposer substrate can be designed in a different top and bottom pitch to connect top mobile memory and bottom packages, respectively. With this structure, die size limitations can be overcome by using finer interconnection pitch, providing the flexibility to allow any memory interface pitch application. In addition, through this developed result, not only the package warpage/coplanarity control and reliability characterization are illustrated, it also demonstrated this enabling technology of high bandwidth fcPoP as a highly integrated, miniaturized and low profile 3D packaging solution.

Package on Package (PoP) components offer a low cost, high performance solution for stacking of a logic device with memory. There are a number of challenges in the final assembly at the Electronic Manufacturing Services (EMS) facility. An assembly process has been developed for a Bond Via Array (BVA) PoP package having 14mm x 14mm body size with a topside memory module and a bottom logic module. In this PoP design, the solder ball interconnects between the top memory module and bottom logic module has 5 outer rows having 1020 I/O with a 0.24 mm pitch. The solder ball interconnects between the bottom logic module and the PCB is a patterned array having 916 I/O with a 0.4mm pitch. A special focus on this work was the optimization of the stacking process of the memory solder balls to make good interconnections to the BVA wires protruding from the bottom logic package. Topics covered for process evaluation will be vision systems, yield, package alignment and placement, voiding and major-defect identification such as bridging, opens-insufficient solder. Process issues related to solder volume, substrate coplanarity and x-ray inspection techniques will be presented. Finally design recommendations, reliability data and rework techniques will be reviewed.

Higher packaging density is driven by the multifunctional requirements and size shrinkage in handheld applications, which was greatly improved by the 3D packaging technologies. Package-on-package (POP) is one of the 3D packaging solutions, in which components can be fully tested good prior to integration. However, the package warpage due to mismatch of materials properties is a greater challenge for POP than other packaging types during stack process of POP components. Initial components warpage may affect the assembly processes due to the non-coplanarity. The value and direction of warpage could result in the solder joint openings and affect the stresses distribution in the device working state. In the study, effects of initial warpage of top component in POP with two components stacked on the assembly and POP working state were investigated by Finite elements analysis (FEA). The different powers of logic die were considered in the analysis, which were applied on the dies as thermal loading under the device working state. The analysis results in this study provide some clues and guideline for the component initial warpage control in POP, which influence the POP assembly yield and reliability in the device working state.

The tremendous growth in smartphones and tablets has been fueled by consumer demand for increased mobility, functionality, and ease of use. This, in turn, has been driving an increase in functional convergence and 3D integration of integrated circuit (IC) devices, resulting in the need for more advanced and sophisticated packaging techniques. In particular, the integration of the application processor (AP) and dedicated memory has become increasingly complex. Smartphones and tablets have become virtual streaming devices requiring low power, high bandwidth memory (HBM). For quality, high-speed video and multi-tasking applications, the memory interface to the AP must have superior signal integrity to minimize crosstalk and insertion/return losses. In addition, the thermal management of the processor must allow the maximum clock speed and duty cycle for high-performance applications. Finally, to conserve battery life for the mobility device, the power distribution to the processor must be as efficient as possible. This creates a significant challenge for the semiconductor packaging industry to meet these demanding requirements for smartphone and tablet products. This paper introduces a leading-edge high-density fan-out (HD-FO) semiconductor packaging technology that addresses the need for higher levels of integration and improved electrical and thermal performance for mobile applications. This new innovative technique, called Silicon Wafer Integrated Fan-out Technology (SWIFT™) packaging, leverages the fine feature size and thin-film circuit patterning capabilities of wafer-level packaging. In addition, thin-film dielectric photolithography and pattern plating provides a significant reduction in package z-height, which is critical for advanced mobile devices. By incorporating a redistribution layer (RDL)-first/chip-last process flow, there is also an opportunity for yield optimization and cycle-time reduction. This work compares the electrical and thermal modeling results between a conventional Package-on-Package (PoP) and HD-FO SWIFT devices. The results reveal a highly integrated PoP structure with exceptional electrical, mechanical, and thermal performance benefits – compared to conventional organic laminate-based technologies – to meet the growing need for high-performance mobile applications.

Along with the advancement in miniaturizing of mobile devices, typified by smart phones and tablet PCs, the semiconductor PKG substrate installed in these devices is demanded to be thinner and higher in density. As one of the most innovative solutions, the PoP (package on package) technology, which has the three-dimensional construction, has been expanding rapidly in recent years. However, thinner PKG such as PoP tends to warp at the assembly process and cause the decrease in the connection reliability. Therefore ultra low CTE (coefficient of thermal expansion) core materials have been needed as a key solution for the reduction of the warpage for PoP. We have already developed and mass-produced ultra low CTE core material named E-770G (CTE value: 1.8 ppm/°C) for this application. However, the demand for lower warpage is still stronger especially for thinner PKG applications. To meet this requirement, we confirmed that not only low CTE but also lower resin shrinkage control gives big impact to warpage. In this paper, we would like to introduce new ultra low CTE and low shrinkage core material, named E-777G for next generation thin CSP. At the same time, we would like to explain the relationship between the warpage and material properties (CTE and resin shrinkage). E-777G has ultra low CTE and low shrinkage. These properties were achieved by applying our original resin system designed by hard segments and soft segments. Hard segments have a stack structure of aromatic ring and the strong intermolecular force between them, which lead to the ultra low CTE and low shrinkage. Soft segments of low elastic modulus can follow approximately the thermal behavior of glass fabric when heated and cooled. Consequently, the material can show the ultra low CTE which is similar to that of glass fabric itself. As a result, E-777G has achieved the ultra low CTE of 0.7 ppm/°C by TMA method which leads to significant reduction of the warpage. In the cooling process after the reflow, the bottom PKG of PoP shows a convex warpage. It is caused by resin shrinkage of substrate in the cooling process. As the method of decreasing resin shrinkage in the cooling process, we focused on decreasing free volume of the resin. By using molecular dynamics simulation, we designed the most suitable resin composition. Confirming the warpage property, we evaluated the warpage behavior of the bottom PKG before/after assembly process. The bottom PKG using E-777G material showed lower warpage than E-770G. We confirmed that not only the ultra low CTE but also low shrinkage of material effectively contributes to the decrease of the warpage.