- https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830489
2.4GHz, Double-Buffered, 4kb Standard-Cell-Based Register File with Low-Power Mixed-Frequency Clocking for Machine Learning Accelerators
- Jun 12, 2022
- Steven Hsu +8 more
Abstract
A double-buffered, 4kb standard-cell-based register file with measured 2.4GHz operation at 0.65V, 100°C and scalable performance to 3.7GHz at 0.8V is fabricated in a leading-edge CMOS node. Double-buffering, Gray-coded read/write addressing, super-multi-bit macro standard cells, and mixed-frequency clocking enable a measured peak energy-efficiency of 5.73TOPS/W at 0.5V, 0°C with 14%/11% register file read/write power savings and 28% area reduction over conventional ping-pong design.
- # Register File
- # GHz Operation
- # Area Reduction
- # Power Savings
- # Conventional Design
- # Machine Learning Accelerators
- # Leading-edge CMOS
- # Peak Energy-efficiency
- # CMOS Node
- # Learning Accelerators
