5- https://doi.org/10.1109/isscc49661.2025.10904663
37.1 IBM Telum II Processor Design-Technology Co-Optimizations for Power, Performance, Area, and Reliability
- Feb 16, 2025
- David Wolpert +21 more
The IBM zNext's Telum II processor [1] is a full-stack overhaul of its predecessor [2], featuring a modified 5nm Samsung bulk technology [3], new IBM-created standard cell and IP libraries, and a variety of further design-technology co-optimizations (DTCO). While die size grew from <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$530\text{mm}^{2}$</tex> to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$600\text{mm}^{2}$</tex> (1.13×), each chip in the dual-chip module became denser, featuring 1.3T shapes (1.25×), 43B transistors (1.38×), and 38km of wire (1.28×) across 18 BEOL layers. As IBM's first 5nm processor, Telum II was a concurrent hierarchical design effort, with libraries, IP blocks (array / regfile / analog / phy / custom), and all gate-level entities designed simultaneously. These data volume and concurrent design pressures drove a variety of abstraction, modeling, and other EDA innovations in addition to those involving power, performance, area, and reliability targets.
