3D-MID for Space

Current techniques for nondestructive quality evaluation of solder bumps in electronic packages are either incapable of detecting solder bump cracks, or unsuitable for in-line inspection due to high cost and throughput. As an alternative, a solder bump inspection system is being developed at Georgia Tech using laser ultrasound and interferometric techniques [1]. This system uses a pulsed Nd:YAG laser to induce ultrasound in electronic packages in the thermoelastic regime; it then measures the transient out-of-plane displacement responses on the surface of the chip or packages using laser interferometric technique. This paper presents a systematic study on thermo-mechanical reliability of flip chip solder bumps using laser ultrasound-interferometric inspection system and finite element (FE) simulation. The correlation between the failure parameter of solder bumps extracted from FE simulation and the quality degradation results of solder bumps from laser ultrasound testing has also been studied. Accelerated thermal cycling (ATC) tests were performed in two phases on flip chip package (FCP) test vehicles with 63Sn37Pb solder bumps. In phase I, four boards were thermal cycled up to 70 cycles. Every ten cycles, the boards were taken out and FCPs on each board were tested for presence of cracks using resistance and laser ultrasound testing methods. These measurements were repeated every 10 cycles and stopped after 70 cycles. Laser ultrasound testing results show that beginning from 10 cycles, testing values began to increase gradually until 50 cycles when there was a sharp jump (through crack verified at 50 cycles with cross-section). Cross-section was done only after 70 cycles, and the results show that solder bumps at the corners had through cracks, while solder bumps at the center had partial cracks. Phase II studies were refinements of phase I studies. In phase II studies, seven boards were thermal cycled starting from 27 cycles to 56 cycles at an increment of approximate five cycles. After every five cycles, only one board was pulled out and tested in order to track crack initialization and propagation in solder bumps. Smaller thermal cycle increments were used to help determine exactly when cracks initiated and propagated. It was shown that laser ultrasound technique could track solder bump crack propagation induced by thermal cycling. The elastic-plastic-creep and Anand's viscoplastic constitutive models have been used in FE simulation to describe the inelastic deformation behavior of solder bumps. A three-dimension FE model was implemented using ANSYSreg on the same FCP as used in the ATC testing. The stress-strain results were extracted from FE modeling and the inelastic strain energy density (SED) per cycle calculated at the critical solder bump position was used as a failure parameter. It was found that there was a good correlation between inelastic SED extracted from FE simulation and results from laser ultrasound testing.

An automated assembly technique for small optical components has been developed. It concerns components such as, e.g., laser diodes and LEDs, fibers, lenses, beamsplitters, polarizers, mirrors, crystals, prisms, diffractive elements or photodiodes. It is based on the flexible 2-dimensional arrangement of an universal tripod holder (10 x 10 x 4 mm) on a planar mounting plate. Its particular mechanical structure allows to align the optical elements on-line and to attach them to the mounting plate in a one step procedure. The different elements are aligned with an accuracy of +/-1 mu m and attached one after the other. Very good position stability (+/-0,7 mu m, +/-0,2 mad) during the attachment procedure has been achieved by laser point welding. They are optically interconnected by free-space propagation of a light beam with a diameter of up to 8 millimeters. Mass production has been shown with a collimator as test vehicle. The collimator is composed of two elements (laser diode and collimating lens) and is mounted entirely automatically by two co-working robots. Easy prototyping has been shown with the realization of the optical position sensing system featuring a high precision linear magnetic bearing. Flexibility, simple handling, high packaging density and low cost make this new assembly technique suitable to both mass production and protoyping of small opto electronical devices.

The market constantly demands the extension of the functional features of electronic devices and this leads to the application of new materials. Polymers represent an innovative potential due to their favorable properties for packaging. The MID technology represents a new growing potential in the electronic packaging (Forschungsvereinigung and Feldmann, 2004). Metal-polymer bonds are the key issue for this technology. For the quality and reliability of a metal-polymer component the adhesive strength of the metal-polymer composite is a critical factor. Normally, it is usual to pretreat either the polymer or the metal surface by physical or chemical methods to promote strong interactions between metal and polymer. Among the various pretreatment processes the plasma modification of the polymer surface wins a key position (Friedrich et al., 2002). Reactions between plasma species and polymer surface make it possible to form polar groups on the polymer surface. Polar chemical groups like C-OH, CO, CHO, COOH are reactive chemically, can form chemical bonds and therefore can cause an increase of the surface energy and the wetting quality. This work deals with investigation results of the adhesion between polyamide 6 and polyamide 6.6 and typical of MID Technology metals like copper and silver. The following procedure shows the methods and opportunities for the improvement and characterization of the metal-polymer adhesion.

Properties of copper modified polyamide 12-powders and their potential for the use as laser direct structurable electronic circuit carriers

Voiding in solder joints is a common problem that occur in electronic packaging, specifically for bottom terminated component (BTC). Quad Flat No-Lead (QFN) is a good example of BTC component that susceptible to void. Thus, QFN component thermal pads were used as the test vehicle in this voiding assessment. The objectives of this study are to analyze the influence of the variables from every parameter evaluated in the experiment on voiding area in QFN thermal pad solder joint and obtain the best combination of variables that can minimize the total void area percentage inside QFN thermal pad solder joint down to below 5%. In this study, several variables and their impacts on voiding based on the literature review were studied. No clean lead-free solder paste of SAC305 composition was employed in this experiment. Various stencil patterns were tested, including Window-Pane, Round, and Triangle/Polygon. The influence of pad surface finishing of the test board on the voiding reduction was analyzed in this study. The effects of convection reflow of various profiles and atmospheres were also considered. All the variables were setup for the experiment execution which begins by solder paste printing, solder paste inspection, component pick & place, convection reflow soldering, Xray inspection, void data extraction & analysis, and finally void results compilation. The results shown that reflow profile Ramp-To-Spike (RTS) Long Reflow Time High Peak Temperature gave lesser void area % than Ramp-Soak-Spike (RSS) Long Soak and RTS Normal profiles.

With the great environmental concern, lead-free solders gradually replace lead-based solders in electronic packages. However, the relatively short history of lead-free solders makes their reliability database inadequate. In other words, there is an urgent need to establish the reliability information of lead-free solders. In this study, a failure analysis is conducted to investigate the reliability of lead free solders. The test vehicle is the flip chip on board (FCOB) with the size of 8 mm*8 mm*0.29 mm, 0.5 mm pitch and an I/O array of 16times16 balls. The device is chosen for its recent popularity in the semiconductor packaging industry. The device includes the silicon chip, solder balls, polymeric underfill and substrate. The analysis is performed by a 3D finite element model. Both 96.5Sn/3.5Ag and 63Sn/37Pb solders are examined for their reliability by accelerated thermal cycling test (ATC) with temperatures ranging from -40degC to 150degC. This approach is used because solder joints are the weakest interconnection of the FCOB and the thermal stress induced low cycle fatigue due to mismatch in the coefficient of thermal expansion (CTE) is the key failure cause. The steady state forced convection and time- dependent elastic strain conditions are adopted. The reliability prediction is evaluated through the Kanchanomai model for 96.5Sn/3.5Ag solder balls and the Engelmaier model for 63Sn/37Pb solder balls, respectively. The simulation results indicate that the outmost solder joint has the largest Von Mises stress and strain for both lead-free and lead-based solders. The delamination between the chip and substrate is affected by the thermal-stress induced by the mismatched CTE. The reliability for lead-free solder 96.5Sn/3.5Ag can reach to 70% or above of the lead-based 63Sn/37Pb solder.

In view of the challenges faced by remote diagnosis function testing of intelligent networked vehicles, such as complex scenarios, low efficiency, and insufficient abnormal coverage, this paper proposes a set of automated testing technology solutions. By integrating model-driven and keyword-driven methods, combined with hardware-in-the-loop (HIL) simulation and cloud-vehicle communication simulation environment, an automated test framework covering protocol analysis, diagnostic services, exception injection and performance monitoring is constructed. Successfully applied in a vehicle project: 98.3% DTC management, data acquisition and remote control function coverage, 65% shortened the test cycle, 56 deep defects were found, and verify the performance metric of end-to-end latency being less than 1.2 seconds. It has been proved in practice that this solution significantly improves the test efficiency and system reliability, and provides an effective technical path for remote diagnostic testing of intelligent vehicles.

Molded interconnect device (MID) technology is a key enabling technology with growing markets in automotive, communications, consumer electronics through integration with lighting and sensor technologies. The MID technology is yet to be explored for high temperature applications in automotive or consumer lighting. One of the hindering factors for such implementation in the serial production and time to market is the improper electronic and thermal packaging of the light emitting diodes (LEDs) on the MID substrates. This paper addresses the optimization of mold design, surface metallization and soldering process for the effective thermal management of the high-power LED systems. By using a simulation model, the thermal distribution and the resultant decrease in temperatures for varying forward electrical currents in high-power LEDs by design optimization is demonstrated. In addition, the optimization of solder process with respect to solder profile in context of vacuum vapor-phase soldering for void-free solder connections is discussed.

<title>ABSTRACT</title> <p>There has been a lot of interest in the secure embedded L4 (seL4) microkernel in recent years as the basis of a cyber-security platform because it has been formally proven to be correct and free of common defects. However, while the seL4 microkernel has a formal proof of correctness, it does so at the cost of deferring functionality to the user space that most developers and system integrators would deem necessary for real life products and solutions, and use of formal proofs for user space can be prohibitively expensive. DornerWorks took an approach to bypass the need for native seL4 user space applications to develop a representative real-world system for GVSC VEA based on seL4 by enabling its virtual machine monitor functionality for ARMv8 platforms, allowing feature rich software stacks to be run in isolation guaranteed by the seL4 formal proofs. This paper describes that system and the efforts undertaken to achieve real world functionality.</p> <p><bold>Citation:</bold> R. VanVossen, J. Millwood, C. Guikema, L. Elliott, J. Roach, “The seL4 Microkernel – A Robust, Resilient, and Open-Source Foundation for Ground Vehicle Electronics Architecture”, In <italic>Proceedings of the Ground Vehicle Systems Engineering and Technology Symposium</italic> (GVSETS), NDIA, Novi, MI, Aug. 13-15, 2019.</p>

In this article, a prediction method based on a radial basis function neural network and an improved unscented Kalman filter, is proposed to improve the accuracy of position and velocity of the Global Positioning System/Strapdown Inertial Navigation System (GPS/SINS) integrated navigation system, especially in the presence of GPS signal outages. The improved unscented Kalman filter based on the adaptive theory is adopted to enhance the positioning accuracy of the GPS/SINS integrated navigation system when a GPS signal is available. A radial basis function neural network and a non-stationary time series analysis are used to predict and compensate for the positioning error of the GPS/SINS integration in the presence of GPS signal outages to improve the reliability of the navigation system. The effectiveness of the proposed method is verified by the simulation experiment and vehicle test. The simulation and test results show that the proposed method can improve the position accuracy and velocity accuracy in different GPS outage time periods.

Lifi technology was introduced to face the increased demand of wireless applications caused by the drastic increase of users. Light from LEDs are used to transmit the signals. Unlike radio waves, the data transmission using visible light is more efficient with high security defense. Visible light can be used for free of cost is another major reason for its wide application. There is an increase in the usage of Lifi technology in hospital zones and security communications for its un harmful and data security reasons. Communication domain estimates a high increase in demand for Lifi technology in the near future which includes its usage in space and under water communications. Due to few limitations in Lifi technology; it cannot fully replace radio wave transmission technology. Anyway the hybrid model of bringing both wifi and Lifi technology is having a great future demand in the communication world. This review helps the Researchers in Lifi technology to expand their search in this communication technology.

Ni3Sn4 intermetallic compound (IMC) is a critical material in modern electronic packaging and soldering technology. Although Ni3Sn4 enhances the strength of solder joints, its brittleness and anisotropy make it prone to crack formation under mechanical stress, such as thermal cycling or vibration. To improve the plasticity of Ni3Sn4 and mitigate its anisotropy, this study employs first-principles calculations to investigate the mechanical properties and electronic structure of the doped compounds Cex Ni3−xSn4 (x = 0, 0.5, 1, 1.5, 2) by adding the rare earth element Ce. The results indicate that the structure Ce0.5 Ni2.5Sn4 has a lower formation enthalpy (Hf) compared to other doped structures, suggesting enhanced stability. It was found that all structures exhibit improved plasticity with Ce doping, while the Ce0.5 Ni2.5Sn4 structure shows relatively minor changes in hardness (H) and elastic modulus, along with the lowest anisotropy value (AU). Analysis of the total density of states (TDOS) and partial density of states (PDOS) reveals that the electronic properties are primarily influenced by the Ni-d and Ce-f orbitals. At the Fermi level, all Cex Ni3−xSn4 (x = 0, 0.5, 1, 1.5, 2) structures exhibit metallic characteristics and distinct electrical conductivity. Notably, the TDOS value at the Fermi level for Ce0.5 Ni2.5Sn4 lies between those of Ni3Sn4 and other doped structures, indicating good metallicity and conductivity, as well as relative stability. Further PDOS analysis suggests that Ce doping enhances the plasticity of Ni3Sn4. This study provides valuable insights for the further application of rare earth elements in electronic packaging materials.

Power cycling is an accelerated reliability test used to induce package-related failure mechanisms through exposure to cyclic thermal and electrical stress. As SiC devices continue to grow in adoption for high power density, high efficiency applications, packaging material tradeoffs must be clearly understood to develop highly reliable packaging systems suitable to meet the lifetime requirements of an end-application environment. Verification of the degradation experienced by various thermo-mechanical stackups during active power cycling is paramount to optimizing packages for applications which exceed standard junction temperature ratings of 150°C. A comparison of the predominant failure mechanisms and lifetime experienced by three different test vehicles, designed to replicate both standard Si IGBT solder attaches and higher-temperature solder attaches, under high temperature (T j,max = 175°C, ∆T = 80°C), fast (t on < 5 s) power cycling conditions is presented.

In the last half a century, the complexity of electronic systems has undergone a sustainable rapid development stage following the Moore's law: the density of integrated circuits (ICs) was doubled every two years. As a result, electronic devices become more miniaturized in space and contain more power in unit volume. Electronic package has to deal with highly increased I/Os with fine soldering pitch. A symbol of the fast development of the package technology is using staked technique to develop three-dimensional (3D) package from 2D and 2.5D. The representative products are the package-on-package (PoP) technology in which packages are staked and through-silicon-via (TSV) technology in which chips are staked. The PoP has been widely used in handheld products such as cell phones and PDA. The harsh environment in service and high integration in composition have brought big challengers to the design and process of the package. PoP technology has attracted great attentions. The staked composition has largely reduced the length of connection lines between packages. It is also coupled with modules design concept in which different functions can be contained in different packages and thus results in a convenience for efficient production. In view of the advantages, PoP is favored by cell phones and other handheld products. A great deal of work has been done on the general issues. However, given the short life period, detailed studies on specific aspects and individual products have not been covered in full. These include such aspects as the effects of pad design, stencil design and soldering profile on the reliability of PoP systems. The issue for how to increase the pass rate of soldering satisfactory under extreme deformations has also not been seen by the authors in report. PoP has raised challengers to package design. As a staked system, interactions are intensified between packages: the deformation due to the difference of the coefficient of thermal expansions (CTE) will be accumulated and the heat cannot be dispersed through the surfaces between packages. Furthermore, the staked packages become difficult to bend following the PCB as performed by single thin package. All the above factors can deteriorate mechanical damage. So we will work on investigation of the manufacturability and reliability of a PoP system through an integration of modeling, testing and design modification. This includes (i) finite element analysis (FEA) of the PoP system to identify the critical regions and deformation; (ii) experimental test of the PoP system to validate the FEA results; (iii) evaluation of the impact of thermal deformation on the quality and reliability of solder joints to form guidance for detail designs of PoP systems. Agreed results have been achieved from our modeling and testing. The thermal damage to the PoP system has been realized. The effect of manufacturing details of pad, stencil and soldering on the reliability of PoP systems has been analyzed. A guide for design procedure has been offered. Through this integrated investigation, we have obtained a good understanding to the mechanical performance of PoP systems and found the way for how to design relevant details for enhanced reliability. This has practical reference to PoP design and testing. In this paper, we work on the parts of integration modeling: research on printed board's deformation. Finite element method is used to predict the deformation of printed board in different copper case, testing the PCB s deformation by use moire, and correcting finite element model, after we master PCB deformation, we could design PCB such as layout, routing, and wiring to pave the way for the production of POP. Subsequent work with experimental continue to be in a future paper published in succession.

The structure, fabrication, and theory of a three-dimensional planarized optoelectronic clock signal distribution device, based on a thin light-guiding substrate in conjunction with a two-dimensional polymer holographic grating array, are described. We have demonstrated previously a 25-GHz 1-to-42 (6 x 7) highly parallel fan-out interconnect with a signal-to-noise ratio of 10 dB. We present theoretical research that focuses on generating a globally uniform fan-out distribution. An objective function aimed at equalizing the intensities among the fan-out beams is established. For an arbitrary M x N fan-out distribution, there are M + N + 1 sets of holograms needed to be recorded independently to provide the required equal fan-outs. The efficiency of each hologram is determined precisely. The angular misalignment, wavelength dispersion, and spot-size problems are discussed further, together with their tolerance requirements on the size of the photoreceivers integrated on the multichip modules. Employment of 0.25-pitch gradient index (GRIN) lenses as a collimator and as a focusing element is demonstrated experimentally. Optical beam profile manipulation and packaging tolerance are enhanced greatly with GRIN lenses. Finally, clock skew problems associated with the proposed system are discussed, and schemes to minimize the skew are proposed.