42.2: Invited Paper: Multi‐Force Touch Technology Augmenting Capacitive Touch in Displays

The design and analysis of software which implements digital signal processing (DSP) algorithms on multiprocessor systems is examined. The DSP algorithms that are considered exhibit certain characteristics which are common of DSP algorithms used in communication and control systems. The analysis methods developed use linear complexity algorithms to analyze the software that implements the DSP algorithms. The first step involves finding the repeat factors associated with a basic cycle of the algorithm. Using these repeat factors it is straightforward to (1) find the precedence relationships between tasks and finally a feasible schedule for the multiprocessor, and (2) coordinate and organize the efforts to optimize the software. >

Validation of Peripheral Pulse Wave Analysis Technique to Detect Aortic Valve State in Continuous-Flow LVADs1

This paper emphasizes on the design of a fully integrated low-power mixed-signal demodulator for multi-gigabit operations in 90 nm CMOS technology. A 3-bit ADC can be used to convert the analog inputs to digital form. But these baseband ADC's experience clipping distortions. This can be reduced by employing wide automatic gain control (AGC). The front-end of the system includes IQ mixers, a QVCO, frequency synthesizer, and AGC. This constitutes the analog block of the demodulator. AGC consists of Variable Gain Amplifier (VGA), power detector circuit, Differential to single ended amplifier and Operational amplifier. 6-bit current steering DAC is used to digitally control the output power of VGA. In order to recover OOK modulated signals, the analog signal processor (ASP) is used. This paper focuses on the design of fully integrated receiver consisting of broadband demodulator with embedded analog and digital signal processors in deep-submicron CMOS technology.

This paper presents a miniature electromagnetic (EM) sensor node for wireless surgical navigation systems. The sensor node measures the intensity of the EM field originated from the EM field generator placed at the predefined position and determines the position and orientation of the object where the sensor node is attached. The wireless electromagnetic sensor node performs analog and digital signal processing as well as wireless communication. The EM field signal from the generator is detected by the LC resonator circuit, and then amplified and filtered in the analog signal processing subsystem. This analog signal is converted to the digital data, and discrete-Fourier-transform analysis is performed in the digital signal processing subsystem. The analysis results are then transferred to the base station by using wireless communication. The developed sensor node is 8.84 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> in volume while exhibiting the accuracy of 99.58% and 99.92% for position and orientation sensing, respectively.

Background. Far-Field R-Wave (FFRW) oversensing and P wave blanking are the major causes of inaccurate atrial signal classification in current pacemaker (PM) devices leading to inaccurate stored diagnostic information and to inadequate PM reactions like mode-switching or preventive pacing. The prospective and multi-center MARS (Morphology of Atrial Signals) study therefore investigated during daily life the capabilities of Digital Signal Processing (DSP) in an implanted dual chamber PM to improve P-wave classification accuracy. Methods . 55 patients with an implanted dual chamber PM (Vitatron T- or C-series) were included: During 24 hours with daily life activity and a stress test, a Holter ECG collected surface ECG, PM markers and all atrial EGM’s. The DSP algorithm analysed atrial events sensed nearby a ventricular event using the minimum and the maximum amplitude of the digitalized and filtered signal and the maximum and minimum amplitude of the slope signal. After comparing to the characteristics of a normal P wave, each of these atrial signals were then classified as a true atrial signal or FFRW. DSP classification results were then compared to the conventional PM signal classification by three independent reviewers. Results . Classification accuracy for the traditional PM functionality after optimizing blanking and sensitivity settings was 97.1% (19.5–100%) as compared to 99.4% (76.9–100%) using the DSP algorithm (p&lt;0.001). Conclusion . The DSP algorithm significantly improved the classification accuracy of sensed atrial events as an important prerequisite for a correct diagnostic and therapeutic PM function. The herewith presented approach of analysing atrial signals by form and timing may allow to reduce or even eliminate atrial blanking periods thus leading to larger PM sensing windows to prevent from atrial tachyarrhythmia undersensing without an increase in FFRW sensing.

Traditional digital signal processing technology based on DSP and FPGA is more suitable for real-time signal processing, and is limited by data scale and frequency resolution, making it unsuitable for offline data processing, analysis and mining under large-scale data Application. At present, the industrial big data analysis platform can use Spark as a calculation engine for real-time signal processing and offline signal processing acceleration, but the analysis platform lacks mathematical calculation solutions such as digital signal processing suitable for distributed parallel calculation engines. This article is based on time the parity decomposition is selected, and the fast Fourier transform is realized by MATLAB software. Based on an example of the application of the compiled FFT source program, this article analyses the frequency spectrum of discrete-time and continuous-time signals of limited length.

Analog computation is potentially more efficient in certain arithmetic operations since a single wire can represent multiple bits of information, while digital systems retain advantages, for example, in logical operations. However, the use of conventional voltage-domain analog computation [1, 2] is limited due to its poor scalability, design complexity, and the overhead of interface circuits (i.e. ADC/DAC) to a surrounding digital system. Therefore, an alternate technique is required for exploiting the efficiency of analog computation. In this paper, we propose time-domain analog and digital mixed (TDMixed) signal processing, wherein time instead of voltage is utilized as the analog signal. To verify the validity of the TDMixed signal processing, we implement an (32, 8) low-density parity-check (LDPC) decoder in 65nm CMOS. The decoder achieves power and area efficiencies of 10.4pJ/b and 6.1Gb/s/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , respectively.

In this article, we use the interval mathematics and targeted rounding by specific functions to establish a framework for interval quantization. The function approximation FId, that maps x to an interval [x1, x2] such that x1 is the largest floating point number less than or equal to x and x2 is the smallest floating point number greater than or equal to x, is used to establish the sampling interval and the levels of interval quantization. We show that the interval quantization levels (Nj) represent the specific quantization levels (nj), that are comparable, according to Kulisch- Miranker order and are disjoint two by two. If an interval signal X[n] intercepts a quantization interval level Nj, then the quantized signal will be Xq[n] = Nj. Moreover, for the interval quantization error (E[n] = Xq[n] − X[n]) an estimate is shown due to the quantization step and the number of levels. It is also presented the definition of interval coding, in which the number of required bits depends on the amount of quantization levels. Finally, in an example can be seen that the the interval quantization level represent the classical quantization levels and the interval error represents the classical quantization error.

Fast Fourier Transform (FFT) is one of the core algorithms in digital signal processing. The traditional FFT processing method can no longer meet the data processing requirements, so the implementation and optimization of the better performance radix-4 FFT algorithm has very important research value. Based on FPGA technology, this paper proposes a design scheme of radix-4 FFT algorithm processing system. By optimizing the butterfly processing unit, the system realizes a high-performance FFT algorithm processing system with characteristics of faster operation speed, higher calculation accuracy, easy hardware implementation and large capacity compared with the traditional FFT processing method. It is well suited for scientific computing, image processing and other fields.

Context. The digital signal processing is applied in many fields of science, technology and human activity. One of the ways of implementing algorithms of digital signal processing is the development of coprocessors as an integral part of well-known architectures.&#x0D; In the case of developing a pipelined device, the presented approach will allow to use software and hardware tools of the appropriate architecture, provide the faster execution of signal processing algorithms, reduce the number of cycles and memory accesses.&#x0D; Objective. Objectives are design and characterization study of a pipelined RISC-V processor and coprocessor of digital signal processing which performs fast Fourier transform.&#x0D; Method. Analyzing technical literature and existing decisions allow to assess advantages and disadvantages of modern developments and on the basis of which to form the relevance of the selected topic. Model designing and simulation results allow to examine a model efficiency, to determine weak components’ parts and to improve model parameters.&#x0D; Results. The pipelined RISC-V processor has been designed which executes a basic set of instructions. Execution time of assembly program on the single-cycled and the pipelined processors have been analyzed. According to the results, the test program on the pipelined processor is executed in 29 cycles, while on the single-cycle processor it takes 60 cycles. The structure of the coprocessor for the fast Fourier transform algorithm and a set of processor instructions that allow working with the coprocessor have been developed. The number of cycles of the coprocessor based on Radix-2 fast Fourier transform algorithm for 512 points is 2358 cycles, and for 1024 points is 5180 cycles.&#x0D; Conclusions. Conducted researches and calculations have showed that the application of the developed hardware coprocessor reduces the fast Fourier transform algorithm execution time and the load of the pipelined processor during calculations.

Conventional second harmonic current restriction approach is an adopted method which has been implemented to transformer differential protection schemes. Because of unreliable nature of this approach in discrimination between inrush current, internal faults and external faults and due to the saturation of current transformers, we present new features of the differential protection scheme. This helps to determine the feasibility and applicability of the proposed approach in differential protective scheme for power transformer. The Current Transformer Saturation (CTS) phenomenon issue and its revelation is one of the most significant problems in power system protection particularly in the differential protection. In this paper, the saturation phenomenon and its effects on the differential protection are analyzed. Prevalent algorithms in digital signal processing which are implemented in power system cannot correctly recognize this phenomenon. Mal-operation of differential protection relay takes place when saturation in CT is appeared. This paper presents a Third-Difference Algorithm (TDA) for CTS recognition. In order to make comparison between the presented approach and prevalent digital protective algorithm, an identical case study is simulated. Simulation results also show that the TDA is both satisfactory and consistent with expectation. Keywords: Current transformer, Saturation phenomenon, Third-difference Algorithm, Internal and external faults.

Vector rotation is an important component of algorithms in digital signal processing and robotics. Often, the rotation does not require very high accuracy. This study presents a lowoverhead sign‐precomputation‐based architecture for approximate rotation using the coordinate rotation digital computer (CORDIC) algorithm. The proposed architecture is independent of Z ‐datapath, and involves precomputation of the direction of rotation for each micro‐rotation angle. The approach involves selecting the optimal micro‐rotation angles from a set of elementary angles in run time. Careful selection and elimination of the redundant micro‐rotation angles leads to a maximum of three iterations for a majority of the input angles while also simultaneously reaching within 0:45 (of the desired rotation angle). An field programmable gate array (FPGA) implementation of the proposed rotation mode CORDIC on XC7K70T‐3FBG676 Kintex‐7 using Xilinx ISE 13.2 achieves roughly 50% reduction in slice‐delay product and power‐delay product compared to recent designs. An application of approximate rotation to Hough transform‐based lane detection is presented. An efficient algorithm for generation of vote addresses in the parameter space is proposed. It is shown that accurate lane detection is possible along with resource savings using the proposed CORDIC. The proposed architecture reduces the number of additions roughly by a factor of 20 compared with the conventional method of computing a parameter for each feature point.

Assigning service requests in Voice-over-Internet gateway multiprocessors

Wireless communications is evolving in different directions from several starting points. In virtually all cases, evolution has proceeded from analogue systems to digital systems having more capability to cope with the radio environment and at a lower cost. The synergy between digital radio communications and VLSI is revolutionising the design of wireless terminals. More and more these terminals look like dedicated computers capable of executing digital signal processing (DSP) algorithms of extremely high complexity. On the one side, these algorithms are interfaced with the radio channel via the RF analogue front end and antenna of the terminal. On the other side with the user through a microphone, speaker and keyboard. In nearly all cases, the RF subsystem also contains a frequency synthesiser which is again a dedicated digital hardware. The evolution of these terminals is characterised by the disappearance of analogue signal processing components and subsystems and their replacement in the software domain by DSP code which runs on highly optimised hardware for maths. At the same time the DSP number crunching heart of the terminals is going faster, stronger, smaller and cheaper. One should expect that this type of evolution may continue until a point where the analogue hardware will be minimum dealing with signal amplification at RF frequencies, conversion to, and from, near baseband and interfacing via a discrete time analogue circuitry to the DSP domain.

Through the analysis of a data-flow-graph representation of an algorithm, the recent work by P.W. Lee (Ph.D. dissertation, Rutgers Univ., NJ, 1988) produces static, nonpreemptive schedules capable of implementing the algorithm on a multiple-processor system. These schedules are based on the assumptions that algorithms of the type that are typical of a class of digital signal processing (DSP) algorithms are computation bound (as opposed to I/O bound) and that data transfer (I/O operations) occurs instantaneously. This raises the question of the effects on the efficiency of the multiprocessor's utilization as the execution of the algorithm changes from computation bound to I/O bound. In the present work the author examines these effects for two cases of an algorithm (typical of this class of DSP algorithms). These cases are with and without a dominant run-time task, where a dominant run-time task is characterized by a far larger execution time than any other task in the algorithm. It is concluded that the ideal I/O assumption put forth by Lee is valid for software structures that exhibit dominant tasks. >