425-Gbps/λ Dual-polarization IMDD Transceiver

In order to realize receiver (Rx) photonic integrated circuits (PICs) applicable to 400 Gb/s-class coherent passive optical network (PON) systems, we integrated tunable wavelength f ilters (TWFs), PIN photodiodes (PIN-PDs), and optical 90 degree hybrids (90HBs) into Rx PICs fabricated on a commercial standard silicon photonics (SiPh) platform. As a result of device evaluation, we observed characteristics indicating the potential for application in 400 Gb/s-class coherent PON systems. Subse quently, we prototyped Rx assemblies in which the Rx PIC and a digital signal processing (DSP) chip are mounted. When the Rx assembly received a 60-Gbaud dual-polarization (DP) quadrature phase shift keying (QPSK) 200 Gb/s C-band optical signal after 2 km loopback transmission, we achieved an optical received power of −24 dBm at a bit error ratio (BER) of 2×10−2, which corresponds to the forward error correction (FEC) limit. Based on this result, the Rx assembly is suitable for a PON system with a maximum transmission distance of 20 km and up to 16 terminations. Similarly, when the Rx assembly received a DP 16 quadrature amplitude modulation (QAM) 400 Gb/s optical signal, we achieved an optical received power of −6 dBm at the FEC limit. Although some issues remain, these results suggest the Rx assembly can be applied to 400 Gb/s-class coherent PON systems. In the future, we will improve the Rx characteristics by reducing insertion loss of the Rx PICs and will prototype and evaluate transmitter (Tx) assemblies.

In this paper, a low power mechanism with power block management is proposed to reduce the power consumption in DSP chips. Because the digital signal processing (DSP) chips use many functional units in the data-path to achieve parallel processing, the unnecessary functional units are also executed simultaneously, and they dissipate the power. In the paper, we classify the types of instruction sets based on their data flow in the DSP to generate the control signals which active the necessary units in their data-path. The mechanism is called power block management (PBM). We employ particular guarded circuits in the different situations to avoid the actions of unnecessary functional units so as to reduce the power dissipation. The experimental results show that the power consumption can be saved about 14% at the cost of less than 2.7% area increment.

Algebraic Reconstruction Technique (ART) is an age-old method used for solving the problem of three-dimensional (3-D) reconstruction from projections in electron microscopy and radiology. In medical applications, direct 3-D reconstruction is at the forefront of investigation. The simultaneous iterative reconstruction technique (SIRT) is an ART-type algorithm with the potential of generating in a few iterations tomographic images of a quality comparable to that of convolution backprojection (CBP) methods. Pixel-based reconstruction (PBR) is similar to SIRT reconstruction, and it has been shown that PBR algorithms give better quality pictures compared to those produced by SIRT algorithms. In this work, we propose a few modifications to the PBR algorithms. The modified algorithms are shown to give better quality pictures compared to PBR algorithms. The PBR algorithm and the modified PBR algorithms are highly compute intensive, Not many attempts have been made to reconstruct objects in the true 3-D sense because of the high computational overhead. In this study, we have developed parallel two-dimensional (2-D) and 3-D reconstruction algorithms based on modified PBR. We attempt to solve the two problems encountered by the PBR and modified PBR algorithms, i.e., the long computational time and the large memory requirements, by parallelizing the algorithm on a multiprocessor system. We investigate the possible task and data partitioning schemes by exploiting the potential parallelism in the PBR algorithm subject to minimizing the memory requirement. We have implemented an extended hypercube (EH) architecture for the high-speed execution of the 3-D reconstruction algorithm using the commercially available fast floating point digital signal processor (DSP) chips as the processing elements (PEs) and dual-port random access memories (DPR) as channels between the PEs. We discuss and compare the performances of the PBR algorithm on an IBM 6000 RISC workstation, on a Silicon Graphics Indigo 2 workstation, and on an EH system. The results show that an EH(3,1) using DSP chips as PEs executes the modified PBR algorithm about 100 times faster than an LBM 6000 RISC workstation. We have executed the algorithms on a 4-node IBM SP2 parallel computer. The results show that execution time of the algorithm on an EH(3,1) is better than that of a 4-node IBM SP2 system. The speed-up of an EH(3,1) system with eight PEs and one network controller is approximately 7.85.

In this paper, we present a design of modem and vocoder digital signal processor (DSP) chips for CDMA mobile station. The modem chip integrates CDMA reverse link modulator, CDMA forward link demodulator and Viterbi decoder. This chip contains 89,000 gates and 29 kbit RAMS, and the chip size is 10 mm x 10.1 mm which is fabricated using a 0.8 μm 2 metal CMOS technology. To carry out the system-level simulation, models of the base station modulator, the fading channel, the automatic gain control loop, and the microcontroller were developed and interfaced with a gate-level description of the modem application specific integrated circuit (ASIC). The Modem chip is now successfully working in the real CDMA mobile station on its first fab-out. A new DSP architecture was designed to implement the Qualcomm code exited linear prediction (QCELP) vocoder algorithm in an efficient way. The 16 bit vocoder DSP chip has an architecture which supports direct and immediate addressing modes in one instruction cycle, combined with a RISC-type instruction set. This turns out to be effective for the implementation of vocoder algorithm in terms of performance and power consumption. The implementation of QCELP algorithm in our DSP requires only 28 million instruction per second (MIPS) of computation and 290 mW of power consumption. The DSP chip contains 32,000 gates, 32k (2k x 16 bit) RAM, and 240k (10kx24 bit) ROM. The die size is 8.7 mmx8.3 mm and the chip is fabricated using 0.8 μm CMOS technology.

An approach to transmitting two independent microwave vector signals on a single optical carrier with one polarization state based on coherent detection and digital phase noise cancellation is proposed and experimentally demonstrated. At the transmitter, two independent microwave vector signals are modulated on an optical carrier via a dual-drive Mach-Zehnder modulator (DD-MZM). The modulated optical signals are transmitted over a single-mode fiber (SMF) and sent to a coherent receiver. At the receiver, the optical signals are detected where a local oscillator (LO) optical wave generated by a second free-running laser source is also applied. To recover the two microwave vector signals, a novel digital signal processing (DSP) algorithm is developed and applied to eliminate the joint phase noise terms from the transmitter and the LO laser sources as well as the unstable offset frequency between the two laser sources. An experiment is performed. The transmission of two independent 16 quadrature amplitude modulation (16-QAM) microwave vector signals at 4 GHz with a symbol rate of 1 GSymb/s over a 9-km SMF is demonstrated. The transmission performance in terms of error vector magnitudes (EVMs) and bit error rates (BERs) is also evaluated.

A computing structure for control applications in which there is a natural hierarchical structure (allowing algorithms devoted to simple tasks to be placed at the lowest level and complex tasks at the higher levels) is described. The architecture consists of a high-level general-purpose computer (host) and up to eight digital signal processors (DSPs) that can be interfaced with the controlled plant(s). The high-level computer is either a work station or an advanced personal computer with sufficient memory space (RAM and mass memory), equipped with peripherals for implementation of a user-friendly interface, and with the ability to communicate with other computers, perhaps in a local network. The synchronization and the real-time communications between the host and a DSP are implemented by the two memory banks alternatively switched between the host and the DSP. A complete transparency and a minimum overhead result for the tasks running on the DSP.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A compact three-laser source for optical sensing is presented. It is based on a low-noise implementation of the Pound-Drever-Hall method and comprises high-bandwidth optical phase-locked loops. The outputs from three semiconductor distributed feedback lasers, mounted on thermo-electric coolers (TEC), are coupled with micro-lenses into a silicon photonics (SiP) chip that performs beat note detection and several other functions. The chip comprises phase modulators, variable optical attenuators, multi-mode-interference couplers, variable ratio tap couplers, integrated photodiodes and optical fiber butt-couplers. Electrical connections between a metallized ceramic and the TECs, lasers and SiP chip are achieved by wirebonds. All these components stand within a 35 mm by 35 mm package which is interfaced with 90 electrical pins and two fiber pigtails. One pigtail carries the signals from a master and slave lasers, while another carries that from a second slave laser. The pins are soldered to a printed circuit board featuring a micro-processor that controls and monitors the system to ensure stable operation over fluctuating environmental conditions. This highly adaptable multi-laser source can address various sensing applications requiring the tracking of up to three narrow spectral features with a high bandwidth. It is used to sense a fiber-based ring resonator emulating a resonant fiber optics gyroscope. The master laser is locked to the resonator with a loop bandwidth greater than 1 MHz. The slave lasers are offset frequency locked to the master laser with loop bandwidths greater than 100 MHz. This high performance source is compact, automated, robust, and remains locked for days.

The authors present a VLSI multiprocessor architecture for 2-D digital signal processing. This multiprocessor architecture uses a specially designed high-performance DSP (digital signal processor) as a node in a real-time system. The DSP architecture is based on a computational primitive developed by algorithm decomposition techniques and is used for the real-time implementation of 2-D DLSI (discrete linear shift-invariant) systems. As an example, the authors designed a prototype single-chip DSP chip using 1.25- mu m double-metal CMOS technology to operate with a 40-MHz system clock. This multiprocessor system has a simple interconnection network and a simple control scheme. Each processor in this multiprocessor system operates asynchronously, thus providing very efficient operation. This VLSI architecture also has the advantage that the complexity and number of computations per input do not increase as the size of the input data is increased. Thus, very large 2-D data can be processed in near real time. >

Digital signal processing (DSP) has been widely applied in optical communication systems to mitigate various signal distortions and has become one of the key technologies that have sustained data traffic growth over the past decade. However, the strict energy budget of application-specific integrated circuit-based DSP chips has prevented the deployment of some powerful but computationally costly DSP algorithms in real applications. As a result, fiber nonlinearity-induced signal distortions impede fiber communication systems, especially in wavelength-division multiplexed (WDM) transmission systems. To solve these challenges in DSP, there has been a surge of interest in implementing neural networks-based signal processing using photonics hardware (i.e., photonic neural networks). Photonic neural networks promise to break performance limitations in electronics and gain advantages in bandwidth, latency, and power consumption in solving intellectual tasks that are unreachable by conventional digital electronic platforms. This work proposes a photonic recurrent neural network (RNN) capable of simultaneously resolving dispersion and both intra and inter-channel fiber nonlinearities in multiple WDM channels in the photonic domain, for the first time to our best knowledge. Furthermore, our photonic RNN can directly process optical WDM signals in the photonic domain, avoiding prohibitive energy consumption and speed overhead in analog to digital converters (ADCs). Our proposed photonic RNN is fully compatible with mature silicon photonic fabrications. We demonstrate in simulation that our photonic RNN can process multiple WDM channels simultaneously and achieve a reduced bit error rate compared to typical DSP algorithms for all WDM channels in a pulse-amplitude modulation 4-level (PAM4) transmission system, thanks to its unique capability to address inter-channel fiber nonlinearities. In addition to signal quality performance, the proposed system also promises to significantly reduce the power consumption and the latency compared to the state-of-the-art DSP chips, according to our power and latency analysis.

We experimentally demonstrated full-duplex bidirectional transmission of 10-Gb/s millimeter-wave (mm-wave) quadrature phase shift keying (QPSK) signal in E-band (71-76 GHz and 81-86 GHz) optical wireless link. Single-mode fibers (SMF) are connected at both sides of the antenna for uplink and downlink which realize 40-km SMF and 2-m wireless link for bidirectional transmission simultaneously. We utilized multi-level modulation format and coherent detection in such E-band optical wireless link for the first time. Mm-wave QPSK signal is generated by photonic technique to increase spectrum efficiency and received signal is coherently detected to improve receiver sensitivity. After the coherent detection, digital signal processing is utilized to compensate impairments of devices and transmission link.

Over the past decade, real time digital signal processing (DSP) has found several new applications in the biomedical arena. One of these has been in the area of hearing aids. This paper presents quantization analysis of speech processing algorithms, for the hearing impaired, for implementation on Texas Instruments' (TI) TMS320C54x (C54x) fixed point DSP chip. These algorithms were initial implemented on TI's floating-point processor, the TMS320C3x (C3x). Portable C3x units were tested on hearing impaired subjects to assure the efficacy of the various speech processing algorithms. The algorithms that proved successful are currently being ported to the CS4x since this chip is being rapidly reduced in size and is on track to be an extremely low power DSP chip, ideal for eventual use in a behind the ear (BTE) or in the ear (lTE) hearing aid.

We describe a digital technique for measuring the spectral density of resistance fluctuations with simultaneous background subtraction. The technique implements either of two equivalent ac bridge techniques that rely on extremely good orthogonality between the two channels of a dual-phase lock-in amplifier. We use a digital signal processor (DSP) chip and a personal computer in place of both the lock-in amplifier and spectrum analyzer. The digital system can measure sample 1/f noise that is 100 times smaller than the experimental background noise; this performance equals or surpasses that of any analog system. The system is low cost, very flexible, and can function as a stand-alone digital lock-in amplifier or low-frequency spectrum analyzer.

In this paper, noise spectroscopy has been reported earlier as an efficient tool for enhancing the selectivity of biosensors and the analysis was carried out by desktop spectrum analyzer. There were no reports, however, on the efficacy of this method in complex mixture. We have performed here for the first time, noise spectroscopy analysis on complex mixture of food toxin samples and observed that the first cut-off frequencies are indicative of the fact whether the solution has only specific antigen, mixture of specific and nonspecific antigen or no specific antigen at all. To realize a portable immunosensor, we have developed an electronic interface using digital signal processor (DSP) chip of Microchip Technology which has the embedded Fast Fourier Transform (FFT) algorithm for computation of noise spectrum. The entire system has been successfully demonstrated to detect 0.1 fg/ml aflatoxin B1 (AfB1) from a complex mixture with as high as 1000ng/ml non-specific toxins.

Design of power monitoring system for new energy grid-connected operation based on LoRa and 4G technology

In order to obtain excellent varied speed performance of welding robot, the predictive model of motor drive system was established. On the basis of the analysis of the permanent magnet synchronous motor drive system, generalized predictive control method was adopted to control the rotor speed and position of the rotor. Because of the input and output constraint of the system, convex quadratic problem was proposed, and then an active set algorithm was adopted to deal with these constrained input and output. At last, the performance of this method is demonstrated by a real-time implementation using a digital signal processor (DSP) chip on a permanent-magnet synchronous motor with sinusoidal flux distribution. Theoretic analysis and experiments verify the validity and feasibility of this approach.