450mm lithography status for high volume manufacturing

Reticle critical dimension uniformity (CDU) is an important criterion for the qualification of mask layer processes. Normally, the smaller the three sigma value of reticle CDU is, the better is the reticle CDU performance. For qualification of mask processes, the mask layers to be qualified should have a comparable reticle CDU compared to the process of record (POR) mask layers. Because the reticle critical dimension (CD) measurement is based on algorithms like “middle side lobe measurement”, evaluation of the reticle CD-values can not reflect aspects like the sidewall angle of the reticle and variation in corner rounding which may be critical for 45nm technology nodes (and below). All involved tools and processes contribute to the wafer intra-field CDU (scanner, track, reticle, metrology). Normally, the reticle contribution to the wafer CDU should be as small as possible. In order to reduce the process contributions to the wafer intra-field CDU during the mask qualification process, the same toolset (exposure tool, metrology tool) should be applied as for the POR. Out of the results of these investigations the correlation between wafer measurement to target (MTT) and reticle MTT can be obtained in order to accurately qualify the CDU performance of the mask processes. We will demonstrate the correlation between reticle MTT and wafer MTT by use of multiple mask processes and alternative mask blank materials. We will investigate the results of four process-layers looking at advanced binary maskblank material from two different suppliers (moreover the results of a 2X-via layer as an example for a phase-shift maskblank is discussed). Objective of this article is to demonstrate the distribution between reticle MTT and wafer MTT as a qualification criterion for mask processes. The correlation between wafer CD-difference and reticle CD-difference of these mask processes are demonstrated by having performed investigations of dense features of different 28nmtechnology process layers (poly-, active-, contact-, 1X-metal-, 2X-via layers). Referring to the correlation between wafer and reticle MTT, the contribution of the reticle CD-difference to the wafer CD-difference can be used as an evaluation method for the transfer-process of different mask sites.

Critical Dimension (CD) Uniformity is one of the necessary parameters to assure good performance and reliable functionality of any integrated circuit (IC), and towards the advanced technology node 28nm and beyond, corresponding CD Uniformity becomes more and more crucial. It is found that bad mask CD Uniformity is a significant error source at 28nm process. The CD Uniformity on mask, if not controlled well, will badly impact wafer CD performance, and it has been well-studied that CD Uniformity issue from gate line-width in transistors would affect the device performance directly. In this paper we present a novel solution for mask global CD uniformity error correction, which is called as global loading effect correction (GLEC) method and applied nesting in the mask exposure map during the electron beam exposure. There are factors such as global chip layout, writing sequence and chip pattern density distribution (Global Loading), that work on the whole mask CD Uniformity, especially Global Loading is the key factor related to mask global CD error. From our experimental results, different pattern density distribution on mask significantly influenced the final mask CD Uniformity: the mask with undulating pattern density distribution provides much worse CD Uniformity than that with uniform one. Therefore, a GLEC model based on pattern density has been created to compensate the global error during the electron beam exposure, which has been proved to be efficacious to improve mask global CD Uniformity performance. Furthermore, it ’s also revealed that pattern type is another important impact factor, and GLEC coefficient need be modified due to the specific pattern type (e.g. dense line-space only, iso-space only or an average of them) to improve the corresponding mask CD uniformity.

This paper discusses the back-end-of-line (BEOL) layers for a 7 nm predictive process design kit (PDK). The rationale behind choosing a particular lithographic process—EUV lithography, self-aligned double patterning (SADP), and litho-etch litho-etch (LELE)—for different layers, in addition to some design rule values, is described. The rules are based on the literature and on design technology co-optimization (DTCO) evaluation of standard cell based designs and automated place-and-route experiments. Decomposition criteria and design rules to ensure conflict-free coloring of SADP metal topologies and manufacturable SADP photolithography masks are discussed in detail. Their efficacy is demonstrated through successful coloring and photolithography mask derivation for target metal shape layouts, which represent corner cases, by using the Mentor Graphics Calibre and multi-patterning tools. Edge placement errors, misalignment, and critical dimension uniformity are included in the analysis.

This paper describes major contributing factors to the CPI risk and reveals the mitigation strategy successfully applied jointly by GLOBALFOUNDRIES as the silicon supplier and Qualcomm Technologies, Inc., as the customer responsible for packaging. This strategy involves thermo-mechanical modelling, data collection on wafer level using shear test to assess the BEoL-stability, Cu Pillar process development and optimization. The qualification of these process changes had been completed and implemented in volume production. The paper also discusses mechanical wafer level and thermo-mechanical package modeling approaches. A model has been applied to determine the critical factors on BEoL stress/strain during the flip-chip assembly reflow process. These factors include for instance the Cu Pillar bump geometry and stack up. The results of the modelling work were used to set up experiments to further mitigate CPI related failure modes in BEoL on the package level. GLOBALFOUNDRIES and Qualcomm Technologies, Inc., assessed Cu Pillar design related rules such as Cu Pillar diameter and height as well as the Cu Pillar stack up. Process improvements were carried out to reduce the undercut of the barrier underneath the Cu Pillar. The paper reveals how effectively an optimized Cu Pillar design and improved Cu Pillar processing can contribute to the risk mitigation of CPI failure modes in the BEoL for critical package designs and assembly processes with low margin against BEoL fracture during solder reflow. Furthermore, process improvements applied to enhance the BEoL stack strength were investigated and have been implemented in high-volume production. A strong correlation was established between data collected on wafer level to assess the BEoL strength and data collected on package level.

EUV lithography has been brought into mass production. To enhance the yield, improvements in critical dimension (CD) stability, and defectivity still remain of utmost importance. In order to enhance the defectivity performance on contact hole pattern, continuous work has been executed.1 As the result of process optimizations presented at SPIE 2018 for 24 nm contact hole half pitch pattern, single- and multi-closed hole modes as caused by particles included in coating materials, called “in-film particles”, or stochastic failures are the major of defects modes. For defectivity improvement work done this year, optimization of material dispense has been carried out in an attempt to improve the defectivity of single- and multi-closed holes as caused by in-film particles. As the result, totally 19 % of defectivity improvement was obtained as compared with conventional dispense conditions. On the other hand, CD variability is comprised of several components such as wafer to wafer, field to field, within field, and local CD. In addition, not only coater/developer but also scanner, mask, and materials contribute to the variations. In this paper, CD uniformity (CDU) optimization on also contact hole 24 nm half pitch pattern has been executed to improve each component from the standpoint of coater/developer. As a result of the optimization of development process, 13.9 and 6.4 % of field to field and within field CDU improvement have been achieved, respectively.

The Semiconductor Industry Association (SIA) has placed stringent requirements on Next GenerationLithography mask critical dimension (CD) control. A new chemically amplified (CA) positive resist,Shipley XP2040D was evaluated for mask making application. This resist exhibited an extraordinary postexposure bake (PEB) sensitivity, less than 0.6 nm/ C, along with a sub-50 nm resolution. The PEB stabilityin ambient was larger than 4.5 hours and the line-edge-roughness (LER) was less than 2.9 nm. 1. INTRODUCTION Critical dimension (CD) control and uniformity for a SCALPEL mask must be kept within 7 nm (3 ) inorder to meet the SIA Roadmap requirement for 70 nm NGL mask fabrication [1]. Chemically amplified(CA) resists have been considered for NGL mask patterning because of their high resolution, high electronexposure sensitivity and etch selectivity. However, CD variation due to the PEB sensitivity of CA resistcomplicates the mask making process and needs to be minimized.Previous Finite Element Analysis modeling indicates there are PEB temperature gradients across a 200 mmSCALPEL mask and within each membrane of the mask. The thermal variations are due to the combinedcomplex three-dimensional mask structure coupled with the thermal gradients associated with the bakechamber environment. These gradients were experimentally confirmed through the measurement of criticalfeatures across various membranes on the mask array. A CD uniformity of 8-10 nm for inter-membrane and4-7 nm for intra-membrane was observed using a CA negative-tone resist, NEB22[2]. This CD variationwas mainly attributed to the large PEB sensitivity of the resist ( ~8 nm/ C).In order to meet the 7 nm SIA mask budget, CD non-uniformity due to thermal variations must be reduced.One way to minimize the influence of this thermal effect is to use low PEB sensitivity resists. This paperreports on the performance of Shipley XP2040D positive CA resist for 200 mm SCALPEL maskfabrication using the Leica VB6HR 100 KeV e-beam exposure system.

This paper demonstrates a new simulation-based methodology for optimizing critical dimension (CD) bias for contact holes (CH) arrays using several different extreme ultraviolet (EUV) resists that were fully calibrated and verified with physical resist models. The bias for CH was optimized using local CD uniformity (CDU) 3-sigma as a cost function. The CD sigma variations of near-neighbor contact holes were simulated as a function of dose-to-size and mask bias, averaged over a large number of stochastic trials. There is a distinct bias for minimum CD sigma accompanied by an increase in the process window. The results are confirmed with wafer data. We will discuss the results in terms of EUV photon shot noise coupled with resist parameters. The simulation results will be used to predict a parameter space for EUV resist that can optimize line edge roughness (LER)/resolution/process window and CDU. Finally, various tradeoffs will be presented that will enable the process to perform in a high volume manufacturing environment.

To handle upcoming advanced technology nodes, the spec of focus control continues to tighten to satisfy more stringent CD uniformity (CDU). In high volume manufacturing (HVM) nowadays, yield at wafer edge suffers from CDU degradation due to process variation like edge roll-off topography. Advance focus control using diffraction-based focus (DBF) was proposed as one solution; we can apply the focus compensation values, which are determined from DBF measurement. However, the confidence of the focus compensation depends on the accuracy of focus measurement, which is a widely recognized challenge in the industry. In this paper, we have investigated the performance and the accuracy of two different designs of DBF marks by collecting full maps of DBF measurements. The measurement shows different signatures cross wafer from the two designs. For focus accuracy validation, CDU maps of several focus sensitive patterns have been collected and analyzed against the defocus measurement results. Our results demonstrate that with the accuracy improved DBF design and focus correction per exposure (CPE) schematic, the CDU is improved by 20%, at the wafer edge. We find that the dimension of the DBF main pattern (W1) dominates the accuracy of focus measurement. A DBF design guideline is proposed that the main pattern dimension (W1) should be close to device focus sensitive pattern size to capture its defocus signature more effectively. The accuracy of focus measurement benefits from designs that are close to device weak point patterns, which in turn improves the overall CD uniformity.

Lithographic scaling continues to advance by extending the life of 193nm immersion technology, and spacer-type multi-patterning is undeniably the driving force behind this trend. Multi-patterning techniques such as self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) have come to be used in memory devices, and they have also been adopted in logic devices to create constituent patterns in the formation of 1D layout designs. Multi-patterning has consequently become an indispensible technology in the fabrication of all advanced devices. In general, items that must be managed when using multi-patterning include critical dimension uniformity (CDU), line edge roughness (LER), and line width roughness (LWR). Recently, moreover, there has been increasing focus on judging and managing pattern resolution performance from a more detailed perspective and on making a right/wrong judgment from the perspective of edge placement error (EPE). To begin with, pattern resolution performance in spacer-type multi-patterning is affected by the process accuracy of the core (mandrel) pattern. Improving the controllability of CD and LER of the mandrel is most important, and to reduce LER, an appropriate smoothing technique should be carefully selected. In addition, the atomic layer deposition (ALD) technique is generally used to meet the need for high accuracy in forming the spacer film. Advances in scaling are accompanied by stricter requirements in the controllability of fine processing. In this paper, we first describe our efforts in improving controllability by selecting the most appropriate materials for the mandrel pattern and spacer film. Then, based on the materials selected, we present experimental results on a technique for improving etching selectivity.

Progress towards 65 nm next-generation lithography requires unprecedented global CD uniformity, with the actual ITRS 2002 roadmap proposing 4.2 nm 3/spl sigma/ (dense lines) for 65 nm binary masks. Since resolution requirements are satisfied only by using chemically amplified resists (CARs), exposure and post-exposure bake (PEB) are key processes to successful mask making, both introducing global CD errors. Develop and etch processes potentially contribute further global CD errors. The global CD uniformity can be improved significantly by adaptive PEB, especially for CARs showing moderate to strong PEB sensitivity, like NEB22. With the 25-zone hotplate of the APB5500 bake system, facilitated through a novel calibration mask with 25 equidistant temperature sensors within the resist plane, an appropriate temperature profile can be applied during PEB. This temperature profile is automatically calculated by an adaptive optimization algorithm, based on 2-dimensional spline fitting of a CD measurement. A CD-uniformity improvement (dense lines) from 4.8 nm 3/spl sigma/ to 3.9 nm 3/spl sigma/ (/spl cong/20%) on a state-of-the-art production mask is achieved for the chrome layer (ASI, after strip inspection).

A next reticle format is considered from a view point of photomask fabrication process. In order to determine optimal reticle thickness corresponding to 230 mm size, processes feasibility for the thickness are examined. Cr dry etching is studied in terms of plasma condition and patterning accuracy. It is found that Cr dry etching with accurate critical dimension (CD) control is possible with substrate as thick as 12.7 mm. Post exposure bake (PEB) process for chemically amplified (CA) resists is also examined in terms of CD uniformity on substrates. Relationship of substrate thickness and CD uniformity is estimated with PEB controllability and CA resists characteristics. In addition to this, it is demonstrated that actual temperature uniformity for substrate with a thickness of 9 mm is equivalent to that for a present thickness of 6.35 mm. From these results in overall, it is proposed that substrate thickness of 9 mm is feasible for actual photomask production.

Scatterometers are widely used for line/space or 2D structure measurements in both wafer and mask industries. This technology is now gaining more acceptance and is being applied 3D structures such as contacts and pads. Contact CDs and trench depth in photomasks are critical monitoring parameters in mask industry and are discussed here. We are reporting contact CDs and profile results measured from targets from Binary, PSM, and Crless plates. The strategies of model creation such as using simple trapezoid versus more advanced shapes affect how well SWA and footings can be measured and reported from these structures. We are reporting CD and profile information obtained with Scatterometer, and then comparing CD SEM, AFM, and cross section SEM. Multiple different modeling configurations were used with different levels of complexity, and we report on optimum modeling strategy to obtain profile information from 3D structures. The relationship between the modeling strategy versus cross correlation between different parameters is discussed. CD linearity, uniformity, and other correlation parameters to the reference CD SEM tool are reported. Target CDs ranged from 60nm up to 600nm. CD uniformity reported from Scatterometry is 20~30% less than that from CD SEMs. This CD uniformity improvement is due to the fact that scatterometer beam samples dozens to hundreds of samples and 'averages' profile parameters, thus eliminating local effect such as line edge roughness. Contact depth are also measur ed and compared to AFM, in which the bias between the two tools are usually around 3nm or less. In terms of smallest target CD measurable, in this paper we report routine measurement of small contacts with middle CD down to 65nm (bottom CD close to 50nm) with both RP and SE mode. Application of scatterometry method to mask contacts and pads leads to accurate and fast measurement of 3D profiles, and opens up possibility of in-line monitoring of profile information due to the higher runrate compared to traditional metrology tools. Keywords: contacts, scatterometry, metrology, binary, PSM, Crless.

For the development of the most cost effective lithographic solutions for the 22nm node, the lithographic process and relevant requirements on CDU and overlay need to be identified. In this work, 22nm logic SRAM is selected as use case because FinFET SRAM cells are considered to be a potentia l successor to conventional planar transistors for 22nm node chips. We focus on the back-end layers of FinFET SRAM, including metal and contact. Litho solutions simulated under ideal scanner conditions with the ASML Brion Tachyon TM SMO product are shown. This tool co-optimizes a pixilated freeform source and a continuous transmission gray tone mask based on merit functions of edge placement error. Per scenario, these simulations result in a set of preferred litho solutions with respective source and mask. These solutions have to comply with an imaging metric characterized by MEEF and common PW based on typical fab requirements. In a second step the previously generated solutions are evaluated for CDU analysis using realistic scanner error budget. The purpose is to predict the CDU performance of scanner, process and reticle in order to identify the major contributors for every scenario solution. Keywords: source mask optimization (SMO), single exposure (SE), double exposure (DE), double patterning technology (DPT), Litho-Etch-Litho-Et ch (LELE), CD uniformity (CDU), Fin Field Effect Transistor (FinFET)

In this work, the effect of exhaust condition during Post Exposure Bake (PEB) on the critical dimension (CD) performance has been investigated for different DUV resists. Two kinds of PEB chamber cover designs have been tested to see the influence of exhaust flow on CD. It has been found that cleaning and adjusting of PEB exhaust flow will change the resist CD. To confirm the impact of PEB exhaust condition on production, resists for both lines and contact holes are verified by scanning electron microscope (SEM).

Model-based breakdown of resist and mask contributions to local CDU for sub-30-nm contact holes in EUV lithography