A 0.9-V microcontroller for portable applications

As an important factor for long-term jitter in clock synthesis and distribution, reference spurs result from circuit mismatch and nonlinear effects that induce periodic perturbations in phase-locked loops (PLLs). In this paper, a PLL with built-in static phase offset (SPO) detector and charge pump current trimming for self-calibration circuits is proposed. By adjusting the charge pump current ratio determined by an SPO detector, minimum and maximum improvements of 12dB and 22.99dB in reference spur suppression can be achieved. The best improvement reduces the integrated jitter by 10% over a 10kHz to 10MHz bandwidth. The technique is demonstrated for a PLL output frequency from 400 MHz to 1 GHz. The ring oscillator based PLL is designed with 200 KHz bandwidth and 70 degree phase margin. Measurement results from chips across different corners are provided to verify the calibration technique.

In this paper, we present a systematic methodology for designing Reconfigurable Machine Tools (RMTs). The synthesis methodology takes as input a set of functional requirements — a set of process plans and outputs a set of kinematically-viable reconfigurable machine tools that meet the given design specifications. We present a mathematical framework for synthesis of machine tools using a library of building blocks. The framework is rooted in (a) graph theoretic methods of enumeration of alternate structural configurations and (b) screw theory that enables us to manipulate matrix representations of motions to identify appropriate kinematic building blocks. The methodology described in this paper provides a mathematical framework to address dynamic stiffness, and accuracy prediction of the kinematically-viable designs that are generated by the synthesis procedure. This methodology has been implemented in a program, called PREMADE (PRogram for REconfigurable MAchine tool DEsign), and the results are validated against commercial machine tool designs.

The clock frequency for microprocessors can be de-coupled from external logic and memory speed when a phase-locked loop (PLL) clock frequency generator is integrated on chip to synthesize the higher internal clock frequency from a lower frequency external system clock, and improve I/O timing by eliminating (deskewing) delay through the on-chip clock distribution network. Microprocessor clock frequencies are increasing faster than process technology performance improvement by reducing the number of gates between latches. This increases the ratio of flipflops or latches to logic gates, and together with the fact that approximately twice the number of logic gates are used with each new architecture, leads to significant increase in clock capacitive load and power. This trend also drives up the delay in distributing and buffering the clock around the microprocessor to more than 50% of the clock cycle. This work identifies and minimizes major contributions to jitter and skew in the complete clock generator that consists of a PLL operating with the distribution network, for a 203mm/sup 2/ 300MHz microprocessor.

A systematic and robust approach to generating complex protein nanomaterials would have broad utility. We develop a hierarchical approach to designing multi-component protein assemblies from two classes of modular building blocks: designed helical repeat proteins (DHRs) and helical bundle oligomers (HBs). We first rigidly fuse DHRs to HBs to generate a large library of oligomeric building blocks. We then generate assemblies with cyclic, dihedral, and point group symmetries from these building blocks using architecture guided rigid helical fusion with new software named WORMS. X-ray crystallography and cryo-electron microscopy characterization show that the hierarchical design approach can accurately generate a wide range of assemblies, including a 43 nm diameter icosahedral nanocage. The computational methods and building block sets described here provide a very general route to de novo designed protein nanomaterials.

Design of an optical pattern in a light-guide panel (LGP) has relied on empirical methods. However, the characteristics of developing liquid-crystal display (LCD) products such as frequent design modifications, various design conditions, and a short development period make it difficult for the empirical design approach to cope with various design requirements for size, shape, and optical performance of the LCD products. The most important tasks for the design of LGPs are improving average illuminance and the uniformity of the backlight unit. To meet these requirements, a design for an incoupling and an outcoupling part of the LGP is presented. These two parts can be designed in two separate phases: the first for the incoupling part and the second for the outcoupling part. The shape of serration in the incoupling part was first determined by design of experiments, and the dot patterns in the outcoupling part were subsequently determined by a density-based approach with progressive quadratic response surface modeling. Using this design approach, the illuminance was increased from 2241 lx in the initial design to 2299 lx in the optimal design, and its uniformity also increased from 38% to 82%.

In this manuscript, we propose a robust phase locked loop (PLL) using an adaptive, low current-mismatch charge pump in 180nm UMC MPW RF process targeted for internet of things (IoT) applications. The PLL operates over a supply voltage range of 1.3V–1.8V, generating locking frequencies in the range 500 MHz to 1.5 GHz. The proposed charge pump limits the variation in charging and discharging currents to 0.03% of its biasing value, which is designed to be 34.7uA, for change in control voltage from 0.4 V to 1.1 V. Power consumption of the PLL is limited to 2.3mW at 1.8V supply voltage and reduces to 0.9mW for a supply voltage of 1.3V. A 10bit successive approximation register analog to digital converter (SAR ADC) is operated using the proposed PLL and the effect of variation in frequency on its output is demonstrated.

Standardized and modular microfluidic platform for fast Lab on Chip system development

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Buckling is exploited to design a new class of three-dimensional metamaterials with negative Poisson's ratio. A library of auxetic building blocks is identified and procedures are defined to guide their selection and assembly. The auxetic properties of these materials are demonstrated both through experiments and finite element simulations and exhibit excellent qualitative and quantitative agreement.

One of the key selling points of the next-generation network (NGN) architecture is that it facilitates the rapid deployment of numerous applications onto the same core infrastructure. Before this advantage can be fully realized, however, new methods for traffic estimation are needed to assess the performance impact of new applications and ensure adequate quality of service (QoS). We have created a method to assist network operators with such estimates as part of comprehensive design, capacity planning, or business case analyses. The method identifies the key input parameters that impact traffic, provides a library of application building blocks, assembles them to model new applications quickly, and provides a method for calculating the aggregate signaling and bearer traffic for a given set of applications. In this way, a new network model for each application can be created quickly, and the impact of introducing a new set of applications can be estimated without requiring detailed systems engineering expertise on each aspect of the network.

Dynamic system simulation of small satellite projects

Shape-anisotropic colloids: Building blocks for complex assemblies

We present the design and test results of a novel data transmitter ASIC operating up to 20.48 Gbps with 4-level Pulse-Amplitude-Modulation (PAM4) for particle physics experiments. This ASIC, named GBS20, is fabricated in a 65 nm CMOS technology. Two serializers share a 5.12 GHz Phase Locked Loop (PLL) clock. The outputs from the serializers are combined into a PAM4 signal that directly drives a Vertical-Cavity-Surface-Emitting-Laser (VCSEL). The input data channels, each at 1.28 Gbps, are scrambled with an internal 27-1 Pseudo-Random Binary Sequence (PRBS), which also serves as a frame aligner. GBS20 is tested to work at 10.24 and 20.48 Gbps with a VCSEL-based Transmitter-Optical-Subassembly (TOSA). The power consumption of GBS20 is below 238 mW and reduced to 164 mW in the low-power mode.

This paper will present an investigation into the phase detector of a 27 GHz phase-lock loop (PLL) clock multiplier using a 0.18 - mum CMOS process. The phase detector is one part of a multi-faceted project involving the development and verification of the various components composing the phase-lock loop. A low multiplication factor has been selected that provides a benefit in the multiplicative phase noise contribution, requiring a high-speed frequency divider and phase detector. The challenges of developing stable, low-jitter clock sources become greater as the operating frequency is increased. With the integration of digital and analog circuits CMOS technologies are a preferred solution because of their documented high-frequency performance and well-established manufacturing base. A study of the non-ideal performance (i.e., non-90deg phase offset for a 0 V control voltage output in the phase detector) has been undertaken; the offset may be lessened with an increase in the local oscillator switching core gate-source voltage. Simulated and measured results for a Gilbert cell phase detector realized in the TSMC 0.18-mum CMOS process and operating at 6.75 GHz are presented

Multi-core programming is no more a luxury; it is now a necessity, because even embedded processors are becoming multi-core. However, the state-of-the-art techniques such as OpenMP and the Intel Threading Building Block (TBB) library are far from user-friendly due to the tedious work needed in explicitly designing multi-core programs and debugging. At the present days, a solution for above problems will be that to enhance the abstract level of multicore embedded software design. By leveraging on the expertise gained from Verifiable Embedded Real-Time Application Framework (VERTAF), we propose a Multi-Core version of VERTAF, called VERTAF/ Multi-core (VMC in short). VMC is an integrated development environment for multi-core embedded software architecture. Developers would be able to 1. describe their system requirements with SysML by using this environment, 2. model their design with SysML standard notation, 3. automatically apply a pattern structure into their design for a high quality multicore embedded system, 4. generate source code through a well-designed model; 5. map to different hardware architecture as assigned by the model, and 6. finally we can test the code.Using the model driven architecture (MDA) design flow in SysML, we saw a significantly improvement on productivity and quality of a multicore embedded programming over traditional approach.