A 2:1 switched-capacitor DC–DC converter for low power circuits

In recent years, a system using renewable energy has attracted attention, and power converters with high power efficiency and low cost are required. Dual Active Bridge (DAB) DC- DC converters are attracting attention because of their high power-efficiency due to Zero Voltage Switching (ZVS) operation over a wide load range. However, when the voltage input/output ratio is different from the turns ratio of the transformer, there is a disadvantage that the ZVS operation cannot be achieved at light loads, and the power efficiency drops. Therefore, this paper proposes a digital control method that can improve power efficiency at light loads regardless of the voltage input/output conversion ratio. In the experiment, it was confirmed that the power efficiency at light loads could be improved by about 10% when the input/output ratio is 200V / 150V, 150V / 100V, and 125V / 75 V.

This paper presents a 2/3 step-down switched-capacitor DC-DC converter with integrated NMOS-LDOs in both charging and discharging phases to suppress the output voltage ripple. A gate driving technique implementing adaptive gate slope and gate pre-charge is proposed to reduce the switching noise during phase transitions and assist the turn-on of the regulation transistors, respectively. Good load regulation and fast transient response are achieved due to the high open loop gain and bandwidth. Simulation results show that the output voltage ripple is less than 0.5 mV when delivering 100 mA output current. The converter achieves peak efficiency of 83.3% and over 80% across a load current range of 5 mA to 130 mA.

The Weinberg converter is a suitable choice for the battery discharge regulator of a geostationary satellite due to its high efficiency, continuous input and output current, and soft switching of switches and diodes. Nevertheless, this converter has high output current ripple during the commutation period of its output diodes. Therefore, the output RMS current and output voltage ripple are high, which may directly affect the lifetime and total capacitance of bus capacitors and hence, the lifetime and volume of the geostationary satellite. Thus, reducing the output current ripple is important to the design of the geostationary satellite. An improved Weinberg converter with an additional inductor and capacitor is proposed in this paper to reduce the output current and voltage ripple. It features soft switching of all switches, no reverse recovery problems of the diodes, and reduced magnetizing offset current in the coupled inductor. The proposed converter is verified with experimental results from a 750W, 100kHz, 36-50Vdc prototype.

Recently, the bi-directional dc-dc converter has been focused on because of the huge demand for diversification of power supply network including battery. The dual active bridge (DAB) dc-dc converter is one of the most popular circuits for bi-directional applications because of its simple structure. However, power efficiency at light load is the intrinsic problem of a bi-directional DAB DC-DC converter. In this paper, the simple solution with digital operation for the problem is proposed and experiments are performed with 1kW system. This method can reduce a switching surge without other circuits such as snubber and improve power efficiency at light load. Therefore it can reduce loss of switching surge, and improve power efficiency. From the results, 37% maximum power efficiency improvement at light load is confirmed. Furthermore, this method is capable for control in the conventional method in the heavy load range. Consequently, it is possible to reduce the switching surge and realize high power efficiency in a wide load range.

DC–DC power electronics converters are widely used in many applications, such as renewable energy systems. The multistage-stacked boost architecture (MSBA) converter is a large voltage gain converter whose PWM scheme may reduce a percentage of the output voltage ripple, taking advantage of the symmetry of the voltage signals in capacitors (they are triangular waveforms) to have a symmetry cancelation. The switching ripple is unavoidable; the correct selection of components can reduce it, but this may result in a large amount of stored energy (larger size). The selection of capacitors influences the output voltage ripple magnitude. This article proposes a design methodology that combines a recently introduced PWM scheme with a numerical optimization method to choose the capacitors for the MSBA converter. The objective is to minimize the output voltage ripple by choosing two capacitors simultaneously while ensuring the constraint of a certain (maximum) amount of stored energy in capacitors is not overpassed. The internal optimization was performed with the differential evolution algorithm. The results demonstrate that the proposed method that includes numerical optimization allows having a very low output voltage ripple with the same stored energy in capacitors compared to the traditional converter. In a design exercise, up to 60% reduction was observed in the output voltage ripple with the same stored energy in capacitors.

In this paper, the operational of step-up dc-dc converter with high voltage efficiency is analyzed. The amount of critical inductance is calculated between continuous conduction mode (CCM) and discontinuous conduction mode (DCM).In addition, the amount of critical inductance is computed between complete inductor supply mode (CISM) and incomplete inductor supply mode (IISM). Moreover, the output voltage ripple (OVR) is analyzed in definite limitation of input voltage and output load resistance. The maximum output voltage ripple (MOVR) is calculated based on computed converter parameters and ultimately for obtaining minimum ripple of maximum output voltage, the amount of minimum inductance should be computed. The simulation result in software PSCAD/EMTDC is also presented for reconfirming and proving the obtained mathematical theories.

DC-DC converters are used to convert and regulate voltages depending on the requirement of the specific load. There are two types of DC-DC converter: (1) linear regulators and (2) switching regulators. A linear regulator has a small output voltage ripple but its power efficiency degrades when the difference between the input voltage and output voltage increases. On the other hand, the switching regulator has better power efficiency compared to the linear regulator. The switching regulator can convert wide range of input voltages while maintaining high power efficiency and it can also step-up voltages which a linear regulator cannot. The drawback for switching regulator is the need for control circuit that controls the switches and regulation. The switching regulator has also the problem of relatively larger output voltage ripple, which is not suitable for sensitive circuits. In this paper, a hybrid topology was proposed to combine the advantages of the two DC-DC converters. From the simulation of the three converters, the linear regulator only has an efficiency of 28.058% while the switching regulator and hybrid power converter have efficiencies of 49.0881% and 45.6753%, respectively. In addition, input voltages from 0.5V to 5V were tested on the three regulators that would result in a regulated output voltage of 1V. The linear regulator can only regulate voltages above 1V and the PMOS transistor used has a operating voltage of 2.5V which limits the upper voltage boundary of the linear regulator to 3.5V. The switching regulator can regulate wider range of input voltages but due to power loss across the converter, the switching regulator cannot produce a constant output voltage of 1V when the input voltage ranges from 0.5V to 0.7V. The three converters were designed and implemented in a 65nm CMOS process.

A fully integrated multiphase switched-capacitor DC-DC converter with PFM control and charge sharing loss reduction

<p>A DC-DC converter is used to convert from one DC voltage level to another DC voltage level. The output voltage may be increased or decreased when compare to the input voltage based on the circuit topology. DC – DC converters are mainly used as a regulated and isolated power supplies in many applications. Regulated dc power supplies are needed for most analog and digital electronic systems. Most power supplies are designed to meet some or all of the following requirements:</p> <p><strong>Regulated output: </strong>The output voltage must be kept constant with respect to the change in output loading.</p> <p><strong>Isolation: </strong>The output may be required to be electrically isolated from the input.</p> <p>In addition to these requirements, common goals are to reduce power supply size and weight and improve their efficiency. A few applications of DC-DC converters are where 5V DC on a personal computer motherboard must be stepped down to 3V, 2V or less for one of the latest CPU chips; where 1.5V from a single cell must be stepped up to 5V or more, to operate electronic circuitry. The main focus in this paper is to generate dc voltage from a one level to other level with minimum loss. The need for such converters has risen due to the fact that transformers are unable to function on dc.</p>

This paper describes a CMOS pulse frequency modulation (PFM) buck converter employing a digitally programmable voltage level-shifting technique capable of adjusting peak inductor current and output ripple voltage for different load currents. The conventional PFM buck converters employ either an adaptive delay time control circuit or a fixed delay time control circuit to control output ripple voltage and power efficiency with the switching frequency. However, they suffer from a large peak inductor current, resulting in reduced power efficiency. The digitally programmable voltage level-shifting circuit, based on a common source amplifier, is capable of sensing inductor current through the voltage drop caused by on-resistance of the power switch, and can control peak inductor current. The precision needed to control the magnitude of the peak inductor current can be obtained with the number of bits in the digitally programmable voltage level-shifting circuit that are dependent on the input common mode range of the comparator. Employment of one comparator with pre-control logic and post-control logic circuits allows the proposed circuit to improve power efficiency by removing additional circuits, compared with the conventional PFM buck converters. The proposed converter was implemented with a 180 nm CMOS process. The effective chip size of the core block occupies 900μm × 590μm. The proposed PFM mode buck converter with a precision of four bits to control peak inductor current is capable of accommodating an input voltage range of 2.7–3.3 V, and can produce output voltage of 1.2 V. The operational switching frequency measured is on the order of several to several hundred kHz, the load current range is under 150 mA, and the measured output ripple voltage varied, depending on the digital programming status. The measured power efficiency ranged between 70 and 84%.

This paper presents a new full-swing BiNMOS gate with improved power efficiency, superior power consumption with supply voltages down to 1.2V and significantly reduced layout area. The new circuit was compared with bootstrapped-based BiCMOS logic styles, and the standard CMOS logic style. Low-power methodology was used for the optimization of all gates. Tests have been performed at various power supply voltages (0.9V-3V), with various output load capacitances (0.1pF-1pF), at 50MHz frequency and 27°C temperature. At 1.2V and output loads 0.1pF to 0.81pF, the new circuit has up to 2.8 times better power efficiency than the best bootstrapped BiCMOS style reported and consumes 20%-49% less switching power. Under optimal conditions (V dd = 1.6V), the new design has up to 37% higher power efficiency than conventional CMOS logic for loads 0.4pF to 1pF and up to 112% better power efficiency than the best reported BiCMOS style for output loads 0.1pF-0.95pF. Test circuits have been designed and fabricated with 0.8 µm BiCMOS technology with V thn = 0.8 V and V thp = -0.9 V.

Fluctuant irradiance conditions constitute a challenge in front of a proper battery charging process, when originated from a PhotoVoltaic Array (PVA). The behavior of the PVA under such conditions (i.e., reflected by a disturbed PV characteristic curve) increases the complexity of the total available power’s extraction process. This inconvenient fact yields eventually to a decreased overall efficiency of PV systems, especially with the presence of imprecise power-electronics involved circuits. Accordingly, the purpose of this paper is to design a complete battery solar charger, with Maximum Power Point Tracking ability, emerged from a PVA of 1.918 kWp, arranged in Series-Parallel topology. The targeted battery is of Lithium-Ion (Li-I) type, with 24 VDC operating voltage and 150 Ah rated current. The design began by configuring an interleaved synchronous DC-DC converter to produce a desired voltage level, with low inductor ripple current and low output ripple voltage. The DC-DC converter is in turns condemned by a modified Perturb and Observe (P&O) algorithm, to ensure efficient maximum power tracking. Progressively, the design encountered a layout of the bi-directional DC-DC converter to ensure safe current charging values for the battery. Under the same manner, the role of the bi-directional converter was to plug the battery out of the system, in case when the Depth of Discharge (DoD) is below 25%, thus sustaining the life span of the battery. The entire setup of the proposed sub-systems then leads to the relatively fastest, safest, and most reliable battery charging process. Results show an effectiveness (in terms of PV power tracking) ranging from 87% to 100% under four swiftly changing irradiance conditions. Moreover, this paper suggested the design’s future industrialization process, leading to an effective PV solar charger prototype.

Optimizing power efficiency for 3D stacked GPU-in-memory architecture

Improving power efficiency (PE) and reducing roll-off are of significant importance for the commercialization of white organic light-emitting diodes (WOLEDs) in consideration of energy conservation. Herein, record-beating PE of 130.7 lm W−1 and outstanding external quantum efficiency (EQE) of 31.1% are achieved in all-fluorescence two-color WOLEDs based on a simple sandwich configuration of emitting layer consisting of sky-blue and orange delayed fluorescence materials. By introducing a red fluorescence dopant, all-fluorescence three-color WOLEDs with high color rendering index are constructed based on an interlayer sensitization configuration, furnishing ultrahigh PE of 110.7 lm W−1 and EQE of 30.8%. More importantly, both two-color and three-color WOLEDs maintain excellent PEs at operating luminance with smaller roll-offs than the reported state-of-the-art WOLEDs, and further device optimization realizes outstanding comprehensive performances of low driving voltages, large luminance, high PEs and long operational lifetimes. The underlying mechanisms of the impressive device performances are elucidated by host-tuning effect and electron-trapping effect, providing useful guidance for the development of energy-conserving all-fluorescence WOLEDs.

A monolithic current-mode CMOS DC-DC converter with integrated power switches and a novel on-chip current sensor for feedback control is presented in this paper. With the proposed accurate on-chip current sensor, the sensed inductor current, combined with the internal ramp signal, can be used for current-mode DC-DC converter feedback control. In addition, no external components and no extra I/O pins are needed for the current-mode controller. The DC-DC converter has been fabricated with a standard 0.6-/spl mu/m CMOS process. The measured absolute error between the sensed signal and the inductor current is less than 4%. Experimental results show that this converter with on-chip current sensor can operate from 300 kHz to 1 MHz with supply voltage from 3 to 5.2 V, which is suitable for single-cell lithium-ion battery supply applications. The output ripple voltage is about 20 mV with a 10-/spl mu/F off-chip capacitor and 4.7-/spl mu/H off-chip inductor. The power efficiency is over 80% for load current from 50 to 450 mA.