A 3DES implementation especially for CBC feedback loop mode

Distinguishing analysis is an important part of cryptanalysis. It is an important content of discriminating analysis that how to identify ciphertext is encrypted by which cryptosystems when it knows only ciphertext. In this paper, Fisher’s discriminant analysis (FDA), which is based on statistical method and machine learning, is used to identify 4 stream ciphers and 7 block ciphers one to one by extracting 9 different features. The results show that the accuracy rate of the FDA can reach 80% when identifying files that are encrypted by the stream cipher and the block cipher in ECB mode respectively, and files encrypted by the block cipher in ECB mode and CBC mode respectively. The average one to one identification accuracy rates of stream ciphers RC4, Grain, Sosemanuk are more than 55%. The maximum accuracy rate can reach 60% when identifying SMS4 from block ciphers in CBC mode one to one. The identification accuracy rate of entropy-based features is apparently higher than the probability-based features.

Block cipher encryption works on fixed length blocks, usually 128bits. The blocks of data are transformed into encrypted data blocks of identical size using a shared session key. A common feature of some modes of block cipher, such as Cipher Block Chaining mode (CBC), Cipher Feedback mode (CFB), Output Feedback mode (OFB), is the sequential processing. The ciphering process of a block cannot begin until the processing of the preceding block is completed. This feature does not make full use of the processing power in multiple processor systems. In this paper, we proposed a Parallel Block Cipher (PBC) mode, in which blocks of cipher can be processed in parallel. Results of speed performance tests of the PBC mode using various settings are presented and compared with the standard CBC mode. The PBC mode was shown to save 60% of execution time when compared with the CBC mode. Furthermore, the hash value of the data file might be utilized to provide integrity check in addition to encryption using AES128. As a result, the PBC mode has a better speed performance on top of the confidentiality and security provided by the CBC mode.

High-capability electronics systems for a compact, battery-operated computer: Brooke, E, Livengood, R J, Smith, R C and Myers, T FHewlett-Packard J. Vol 34 No 6 (June 1983) p 10

Random-bit sequence generation from image data

Blowfish algorithm (BA) is a symmetric block cipher with a 64-bit block size and variable key lengths from 32 bits up to a maximum of 448 bits. In order to measure the degree of security of blowfish algorithm, some cryptographic tests must be applied such as randomness test, avalanche criteria and correlation coefficient. In this paper we attempt to analyze the security of blowfish using avalanche criteria and correlation coefficient. We analyzed the randomness of the Blowfish output in an earlier paper titled “Randomness Analysis on Blowfish Block Cipher using ECB and CBC Modes”. The results obtained from the analysis of correlation coefficient showed that Blowfish algorithm gives a good nonlinear relation between plaintext and ciphertext while the results of avalanche effect indicate that the algorithm presents good avalanche effect from the second round. C++ is used in the implementation of the blowfish algorithm; MATLAB programming (Mathworks, R., 2012a) is used in the implementation of avalanche effect and correlation coefficient.

A generalized algorithm with efficient architectures for high-speed parallel scramblers with reduced registers is proposed. The algorithm can be applied to any scrambler polynomials with three terms to achieve small numbers of registers and fan-outs. The critical paths only have one register and one XOR gate, which are merged into a dynamic differential circuit for implementation. The results show that more than 50% chip area can be reduced in comparison with literatures, and the power dissipation is only 3.7mW at 1.6GHz with 16 parallel outputs, which is equivalent to 25.6Gbps, using TSMC 0.18 μm CMOS technology.

Software-Defined Internet of Vehicles (SD-IoV) is an emerging technology that is being used in modern intelligent transportation systems (ITS). The ultimate goal of SD-IoV is to provide seamless connectivity to the end-users with low latency and high-speed data transfer. However, due to the increase in the density of the connected IoV using an open channel, i.e., the Internet, the foremost challenges of high power consumption and secure data transfer are inevitable in such an environment. An external eavesdropper may intercept the transmitted message to access the legitimate information over the public channel, i.e., the Internet. Most of the solutions reported in the literature to tackle these issues may not be applicable in the SD-IoV environment due to high computation and communication costs. Motivated from this, in this paper, the problems of high power consumption and secure data transfer in SD-IoV are formulated using mixed-integer non-linear programming (MINLP) with associated constraints. To solve the aforementioned problem, we propose a joint power optimization and secrecy ensured scheme known as <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SecGreen</i> . <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SecGreen</i> has an efficient energy harvesting algorithm using simultaneous wireless information and power transfer (SWIPT) to maximize the energy efficiency. Moreover, to mitigate various security attacks, a resilient lightweight secrecy association protocol is designed between vehicle and trusted gateway node of SD-IoV so that only trusted vehicles can communicate with each other and with the nearest base stations. The secrecy association protocol uses security primitives such as– physically unclonable function (PUF), one-way hash function, and bitwise exclusive OR (XOR) operations which are suitable for energy-constraint sensors in SD-IoV. The performance of the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SecGreen</i> is compared with the existing schemes, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Stable &amp; Scalable Link Optimization (SSLO), and Secure &amp; Energy-Efficient Blockchain-enabled (SEEB)</i> respectively. The result shows that when the number of packets across the subchannel increases, the energy consumption increases. Also, the result shows that the proposed scheme attains 22.5% and 20.34% better energy efficiency as compared to SSLO and SEEB schemes, respectively. In addition, the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SecGreen</i> scheme achieves 37.48% and 32.15% higher throughput as compared to SSLO and SEEB schemes. The results obtained show the superior performance of the proposed <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SecGreen</i> scheme in comparison to these existing competitive schemes in the literature.

Blowfish is used in a wide variety of applications, involving large amounts of data, demanding high-speed encryption, flexible key sizes and various encryption modes. Even though the ASIC implementations have better encryption speeds and throughput than FPGA ones, their flexibility is restricted. In blowfish, key generation and encryption stages function disjointedly rendering it suitable for dynamic reconfiguration. Fiestal network of the algorithm is better suited for inner loop pipelining and loop folding. Combining these architectural features with dynamic reconfiguration and replication results in a proficient architecture for blowfish described in this paper as the DRIL architecture. This four-tier architecture, involving both hardware and software designs, focuses on efficient hardware utilization, higher throughput, flexibility and better performance. Further, DRIL is a platform independent architecture. Performance evaluation on the XILINX SPARTAN 2E and VIRTEX 2 devices showed very high utilization of the FPGA device with a throughput of 259.615 x R Mbps on SPARTAN 2E and 515.218 x R Mbps on VIRTEX 2 devices, where R is the replication factor.

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

The authors present a new approach to the critical path analysis of digital circuits with feedback loops. The idea is to first convert a circuit with feedback loops to an equivalent minimum-sized acyclic circuit using a state-minimisation technique of sequential machines and then to perform critical path analysis. The results of experiments illustrate that the proposed method finds critical paths correctly and efficiently in the presence of feedback loops.

An examination is made of the current approaches to sensor line supervision and their relative effectiveness against the range of easily available circumvention techniques is assessed, compared to encrypted line supervision. Features of high security encrypted line supervision, including encryption techniques, interactive polling, the generation of random data, proprietary algorithms and keys, serial numbers and the processing of such an approach are discussed, including the flexibility offered by miniaturization of the microprocessor controlled circuits and modular system design. How an encryption module can be deployed within an overall high security system is highlighted. Examples of practical applications provide insight into the effective and efficient use of this advanced security technology. >

ScPUAK: Smart card-based secure Protocol for remote User Authentication and Key agreement

ABSTRACTThis paper presents two efficient cellular automata based Montgomery AB2 multipliers for exponentiation in finite fields GF(2m) using a polynomial representation. The proposed type I multiplier produces the results in m + 1 cycles with a critical path delay of two 2-input AND gates, two 2-input XOR gates, and one flip-flop using O(m2) area–time complexity. The proposed type II multiplier produces the results in m + 1 cycles with a critical path delay of one 2-input AND gate, two 2-input XOR gates, and one flip-flop using O(m2) area–time complexity. The proposed architectures are highly modular, and consist of regular blocks of AND and XOR logic gates. Exponentiation is more efficiently implemented by applying AB2 multiplication repeatedly rather than AB multiplication. Compared with related works, the proposed multipliers have lower area–time complexity, and computational and include the features of regularity, modularity, and cascadability.

In the current paper, consisting from two parts, are presented both results already published before (but hard for access) and new once. Actuality of this work is firstly in a fact that recently has been obtained a number of new results in area of applied cryptography that are needed both in a clarification and be put into practice. This is namely the main goal of the current paper. The setting problem in the first paper part concerns to a complexity of symmetric cipher breaking while in the second part of the paper is discussed, so called, keyless cryptography, namely: wiretap channel concept, execution of communication channels which allow to provide information security without of key exchange procedure between legal correspondences. In the part widely used methods of applied mathematics, namely: algebra, number, probability and information theories. Computer simulation also used there. A novelty of the first part of work consists in the following: first of all it is clarified the sense of a key lifetime limitation for different symmetric cipher modes, secondly, it is explained an approach of cipher breaking by the use of quantum computers, finely, the key authentication for the Diffie ‒ Hellman protocol based on the mobile device pairing technology is investigated in detail. In the second part of the current paper has been presented a vulnerability of Dean ‒ Goldsmith cryptosystem under some extension of attacks. The main results of this paper are: estimation of the key lifetime of single key for symmetric cipher in CBC mode, clarifying of Grover’s algorithm breaking of symmetric ciphers by brute force attack, development of a method for authentication of Diffie ‒ Hellman values based on pre-distributed sequences, selection of ciphers which allow to execute with Shamir’s protocol without any key sharing in advance, breaking of Dean ‒ Goldsmith protocol under some conclusions, proof the fact regarding of a possible breakability of the key sharing protocol over noiseless communication channels. Practical application of paper results consists in the fact of stimulation the correct choice of ciphers and their parameters in order to provide their resistance to different attacks and more attention to algorithms of keyless cryptography.

In this paper, a unified algebraic transformation approach is presented for designing parallel recursive and adaptive digital filters and singular value decomposition (SVD) algorithms. The approach is based on the explorations of some algebraic properties of the target algorithms' representations. Several typical modern digital signal processing examples are presented to illustrate the applications of the technique. They include the cascaded orthogonal recursive digital filter, the Givens rotation-based adaptive inverse QR algorithm for channel equalization, and the QR decomposition-based SVD algorithms. All three examples exhibit similar throughput constraints. There exist long feedback loops in the algorithms' signal flow graph representation, and the critical path is proportional to the size of the problem. Applying the proposed algebraic transformation techniques, parallel architectures are obtained for all three examples. For cascade orthogonal recursive filter, retiming transformation and orthogonal matrix decompositions (or pseudo-commutativity) are applied to obtain parallel filter architectures with critical path of five Givens rotations. For adaptive inverse QR algorithm, the commutativity and associativity of the matrix multiplications are applied to obtain parallel architectures with critical path of either four Givens rotations or three Givens rotations plus two multiply-add operations, whichever turns out to be larger. For SVD algorithms, retiming and associativity of the matrix multiplications are applied to derive parallel architectures with critical path of eight Givens rotations. The critical paths of all parallel architectures are independent of the problem size as compared with being proportional to the problem size in the original sequential algorithms. Parallelism is achieved at the expense of slight increase (or the same for the SVD case) in the algorithms' computational complexity.