A 60-GHz sub-sampling frequency synthesizer using sub-harmonic injection-locked quadrature oscillators

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

This paper presents a fast and autonomous injection frequency tracking and locking technique. In the present injection-locking system, a quadrature injection-locked oscillator (QILO) is third harmonically locked to a quadrature voltage-controlled oscillator (QVCO). In the frequency tracking loop, the frequency difference between QVCO and QILO is extracted using the QILO's amplitude modulated (AM) envelope waveform. The AM frequency of the envelope signal bears frequency difference between the two oscillators. The envelope signal is further converted to pulse signal which subsequently drives digital feedback control circuitry to update the QILO's output frequency so that it can track the third harmonic of the injection QVCO. The frequency calibration process is purely autonomous, self-initiating whenever the AM modulated envelope waveform is generated. The feedback signal is primarily processed in the digital domain, resulting in a compact, fast, and power-efficient injection frequency-locked loop (IFLL). By incorporating a phase noise (PN) calibration routine after completing the frequency calibration, the presented IFLL resolves the intractable issue of PN degradation at the edge of the slave oscillator's injection locking range. This results in a large injection frequency tracking range of 26.5-29.7 GHz which is only limited by the QILO's LC tank tuning range. The IFLL realized in 0.13-μm CMOS consumes 2.4 mW with a negligible area penalty. Overall chip size including QVCO, QILO, and IFLL is 1 × 1 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Electromagnetic waves at millimeter-wave/sub-Terahertz (mm-Wave/sub-THz) frequencies (60 GHz ~ 300 GHz) can interact uniquely with gas molecules, and by detecting the frequency responses of the absorption gas cells, the unique spectral patterns of the gas molecules can be identified and detected with high accuracy. As a result, mm-Wave/sub-THz frequency range has attracted growing interest for rotational spectroscopy for its great potential in environment safety, homeland security and health care applications such as air quality monitoring, toxic gas detection and human breath analyses. With a continuous scaling of CMOS technologies, it is feasible to consider CMOS to significantly reduce the cost and size of rotational spectroscopy systems. An ultra-wideband and low-phase-noise mm-Wave and sub-THz signal generation is essential in a rotational spectroscopy system to improve its detection sensitivity. In this dissertation, sub-THz signal generation systems with novel circuit techniques are proposed in CMOS process to generate high purity local oscillator (LO) signals with ultra-wideband from 60 GHz to 280 GHz. Firstly, magnetic-tuning technique for varactor-less mm-Wave/sub-THz oscillators is analyzed and discussed. Based on the results, a dual-band voltage-controlled oscillator (VCO) prototype is proposed to achieve a frequency tuning range from 95.7 GHz to 110.5 GHz with FoM&lt;sub&gt;T&lt;/sub&gt; of -181.7 dBc/Hz while consuming 6.2 mW. In addition, for quadrature signals generation, a transformer coupling quadrature VCO (TC-QVCO) prototype is proposed with a frequency tuning range from 89.4 GHz to 100.9 GHz and phase error less than 2.6°. Moreover, a fundamental sub-THz oscillator prototype is designed and demonstrated near the f&lt;sub&gt;max&lt;/sub&gt; with a peak output power of -12.1 dBm and frequency tuning range from 157.8 GHz to 166.3 GHz, and a 340-GHz push-push oscillator above the f&lt;sub&gt;max&lt;/sub&gt; is also presented. Secondly, an ultra-wideband sub-THz signal generation system is proposed for rotational spectroscopy employing a magnetic-tuning varactor-less quad-band oscillator (QB-VCO), a locking-range-enhanced dual-mode injection-locked frequency divider (DM-ILFD), a power-efficient injection-locked oscillator (ILO) as a driver, and self-mixing-based frequency multipliers (FMs) for frequency extension. The QB-VCO demonstrated a continuous frequency tuning range of 32% at around 70 GHz. The proposed novel dual-mode DM-ILFD achieves a locking-range of 31.8% in the divide-by-2 mode and 41.2% in the divide-by-4 mode, respectively. The signal generation system achieves a record frequency tuning range from 58.8 GHz to 275.6 GHz with FoM&lt;sub&gt;T&lt;/sub&gt; of -190.4 dBc/Hz while consuming only 54 mW. Thirdly, a harmonic extraction technique is proposed to enhance the third-harmonic amplitude and further improve the phase noise performance of the sub-THz LO generation. Based on this technique, a scalable cascaded injection-locked frequency multiplier chain architecture is proposed, which can generate sub-THz signal from a low RF tone. A prototype of a cascaded two-stage ILFM-based sub-THz LO generation is demonstrated with ultra-low power consumption of 2.5 mW. The prototype achieves a frequency tuning range of 23.7% from 153.9 GHz to 195.3 GHz with a phase noise of -106.8 dBc/Hz at 10-MHz offset, corresponding to FoM of -186.5 dBc/Hz and FoM&lt;sub&gt;T&lt;/sub&gt; of -194.1 dBc/Hz. Finally, by employing a radio frequency (RF) sub-sampling PLL (SS-PLL) cascaded with an injection-locked-based mm-Wave LO generation chain, and a sub-THz mixer and push-push extraction for frequency extension, a fully integrated wideband and low phase noise sub-THz frequency synthesizer is proposed for the rotational spectroscopy system. Third-harmonic and fourth-harmonic enhancement methods are proposed for the ILFMs with different multiplication ratios. In addition, a novel frequency tracking loop (FTL) with automatic frequency and amplitude calibration is proposed for the ILFMs. Moreover, a distributed biased technique is also proposed to improve the linearity of the wideband sub-THz oscillator. Designed with 65-nm CMOS process, the sub-THz frequency synthesizer measures a close-loop frequency tuning range from 61.2-to-100.8 GHz, 122.4-to-136.8 GHz and 198.5-to-273.6 GHz, measures a close-loop phase noise from -79.3 dBc/Hz to -95.4 dBc/Hz at 1-MHz offset across the whole tuning range, achieves an integrated jitter of 124 fs, demonstrates an output power of -11 dBm and DC-to-RF efficiency of 0.16% at the frequency above 200 GHz.

This article presents a fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> subsampling PLL (FN-SSPLL) with a phase rotation (PR) technique. The proposed PR-based FN-SSPLL has high output frequency resolution, low phase noise, and low rms jitter. In addition, it obtains an output frequency of fractional times by dithering the phase of the signal fed back into the voltage-controlled oscillator (VCO) to increase the resolution of the output frequency by using sigma-delta modulator (SDM) on the phase-locked loop (PLL). By adopting a subsampling structure, the proposed FN-SSPLL can improve in-band phase noise by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N^{2}$ </tex-math></inline-formula> compared to standard PLLs, and the PR technique can attenuate SDM noise to improve out-of-band phase noise. The proposed PR-based FN-SSPLL was fabricated in a TSMC 65-nm RF CMOS process. The operating frequency range is 27.2–31.2 GHz and the frequency resolution is 24 Hz. Moreover, the reference frequency is 100 MHz and the phase noise is −104.67 dBc/Hz at 400-kHz offset frequency when the carrier frequency is 29.1 GHz. Finally, the measured rms jitter from 1 kHz to 10 MHz is 92 fs, the total power consumption is 23 mW, the supply voltage is 1 V, and the FoMj is −247.1 dB.

Advancements in high-speed wireline and wireless applications are driving the demand for high-performance frequency synthesizers. The conventional sub-sampling phase detector (SSPD) suffers from poor reference spur performance, limiting the overall effectiveness of the sub-sampling phase-locked loop (SSPLL). This article presents a SSPLL incorporating a double-balanced sampling mixer-adopted SSPD (DBSMA-SSPD). The proposed design improves the reference spur by reducing reference feedthrough without requiring external calibration or RC networks. A dual-edge sampling technique is introduced to further enhance in-band phase noise performance. The proposed SSPLL employs an LC-voltage controlled oscillator (VCO) as its core to generate a 2.688 GHz frequency. The design is implemented and fabricated using an industrial 65-nm CMOS process, occupying a total active area of 0.39 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. The SSPLL successfully locks to a 2.688 GHz frequency from a reference frequency of 168 MHz, consuming around 4.1 mW from a 1.2-V supply. The design demonstrates state-of-the-art performance, achieving a measured rms jitter of 207.7 fs over an integration bandwidth of 10 kHz–100 MHz and a measured reference spur of −72 dBc, attributed to the proposed DBSMA-SSPD. Additionally, it achieves an in-band phase noise of −122.16 dBc/Hz at a 200-kHz frequency offset, with a jitter-power figure-of-merit (FOM) of −247.5 dB.

This work presents a D-band frequency synthesizer that can generate an ultra-low jitter output signal over a large frequency-tuning range (FTR). To overcome the structural limitations of conventional sub-terahertz (sub-THz) frequency synthesizers and concurrently achieve a low jitter and a large FTR, we designed a two-stage architecture, in which a 50-GHz band subsampling PLL (SSPLL) with a 3rd-harmonic (HM)-rich class-F voltage-controlled oscillator (VCO) in the first stage interoperated with an HM-boosting frequency multiplier (FM) in the second stage. Designed with a 40-nm CMOS process, this D-band frequency synthesizer exhibited a wide FTR of 11.8%, i.e., 144–162 GHz. Due to its high-gain subsampling phase detector (PD), which can suppress in-band phase noise (PN), and its class-F VCO, which can achieve low out-of-band (OOB) PN, the proposed frequency synthesizer achieved the lowest rms jitter (i.e., 39 fs <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{rms}}$</tex-math> </inline-formula> ). Since the combination of the 3rd-HM-rich class-F VCO and the HM-boosting FM generated a D-band output signal in a power–efficient manner, this work also achieved the best jitter figure-of-merit (FOM) among the state-of-the-art W/D-band frequency synthesizers with an FTR more than 5%.

Highly stable and small size local oscillators is a very important component of any remote sensing, imaging, and telecommunication systems. The key factor influencing the frequency stability is quality factor of the resonance structure. Related close-in to carrier phase noise for offset frequencies above active device corner frequency reduces at least at a rate of 20 dB/decade while offset below corner frequency increases at rate of 30 dB/decade. A new approach in realization of the electrical oscillators is to augment electrical quality factor by optical energy storage components (e.g., fiber optic delay lines and ring resonators) to enhance effective quality factor (Q) to 10^4-10^6, well beyond available electrical Q of 2000 in dielectric resonator oscillators (DRO). Moreover, stability of resonance frequency has been impacted by the environmental induced (e.g., piezo and pyro properties of material) sensitivities. In addition, micro-scale design approaches are reported using multi-mode (both semiconductor and solid state) lasers for low phase noise intermodal oscillations. Finally, forced oscillation techniques of injection locking, phase locking, and mode-locking are attractive to further stabilize electrical and optical oscillation methods. In this thesis, development of broadband stable frequency sources is reported covering both X- and K-band using forced opto-electronic oscillator technique. The broadband frequency tuning is achieved using coarse electrical tuning of YIG bandpass filter combined with fine-tuned optical transversal filter using dispersive delay component and wavelength control of a fiber laser, as optical source. Forced opto-electronic oscillation techniques of self-injection locking (SIL), self-phase locked loop (SPLL), and self-injection locked phase locked loop (SILPLL) are optimized for further frequency stabilization of a frequency synthesizer. In SILPLL application, long delay line is crucial for substantial phase noise reduction; therefore, kilometer long optical fiber delay lines have been used to construct the optical feedback since their loss is extremely low compared to electrical delay lines. Meantime, open loop gain is another key parameter to achieve low phase noise in these feedback systems, as the phase noise reduction is proportional to phase locking loop gain. The phase noise and pull-in time can be greatly reduced in SILPLL as opposed to SIL or SPLL alone. A forced oscillation of fixed frequency DRO at 10 GHz system provide -137 dBc/Hz phase noise at 10kHz offset with under 10 fs aperture jitters, while OEO based X-band and K-band synthesizers provide phase noise of -137 dBc/Hz (&lt;10 fs jitters) and -127 dBc/Hz (&lt;12 fs jitters) at offset 10 kHz respectively in a computer controlled 19" rack-mountable OEO systems. After realization of the desired modular frequency synthesizer, development a compact opto-electronic oscillator system is demonstrated in my PhD study. Monolithic design and testing of multi-section quantum well lasers are reported on 5x2 mm2 InP chip using a commercial foundry service (i.e., SmartPhotonics). The designed lasers consist of 4 major sections of semiconductor optical amplifier (SOA), optical phase modulator (PM) and distributed Bragg reflector (DBR) mirrors. The DBR section provides wavelength selectivity while phase section and gain medium provide output wavelength tuning. An electro-absorption modulator (EAM) is prepared for mode number control using its wavelength sensitive absorption coefficient. The experiments supported predicted performance of this multi-mode laser structure and impact of combined forced oscillation of intermodal oscillations with mode locking method to realize a frequency stabilized and tunable RF signal source. Meantime, forced technique SILPLL and optimum mode locking techniques are applied in order to achieve improved phase noise performance. The free-running inter-modal oscillation frequencies suffers from poor phase noise of -5 dBc/Hz at 1 kHz and -32 dBc/Hz at 10kHz offset around 11.54 GHz, while under forced oscillation a -58 dBc/Hz at 1 kHz offset and -98 dBc/Hz at 10 kHz offset are achieved. A frequency tuning range of 800 MHz is also measured. In mode locked laser operation, the RF beat-notes forced with SILPLL topology provides a better performance. Improved phase noise of -79 dBc/Hz at 1kHz, -110 dBc/Hz at 10 kHz is measured with under 50 fs aperture jitters, while a broadband frequency tuning from 11 GHz to 13 GHz range is measured. The tuning range is potentially to be further improved, if the shared DBR laser pair symmetry could be improved. In summary, this thesis provides the solution for building RF synthesizer using forced opto-electronic oscillator and laser beat-notes oscillation output. The experimental results are corroborated with detailed analytical and numerical modeling to optimize oscillator phase noise performance. The modular design solution shows great stability and low phase noise, while the compact monolithic design solutions are quite attractive for a smaller size. Potential for full integration of multi-mode multi-section MQW laser with optical delay lines are also presented as a logical development path towards a compact frequency synthesizer.

This paper presents a novel fractional-N digital PLL structure with a digitally controlled phase interpolator (DPI) and a time-to-digital converter (TDC). In this structure, a short bit-width DPI and a short bit-width TDC are combined to achieve high phase resolution and low in-band phase noise. Moreover, since the DPI readily achieves 360° phase range and the TDC provides good linearity, no extra complex calibration is needed, which simplifies the design and saves power and chip area. Designed in a 55-nm CMOS technology, the proposed digital PLL achieves -103 dBc/Hz in-band phase noise at 2.4 GHz output frequency. It consumes 2.4 mW from a 1.2-V supply and occupies 0.18 mm2 active chip area.

A 6.6 mW 1.25–2.25 GHz low phase noise PLL frequency synthesizer based on wide tuning range Class-C VCO

This paper proposes a sub-harmonic injection-locked frequency synthesizer with frequency calibration scheme for millimeter-wave Time-division Duplexing (TDD) transceivers. The proposed synthesizer is capable of supporting all 60 GHz channels (58.1-65 GHz) including channel-bonding defined by 60 GHz wireless standards for short-range high-speed wireless communications. In order to guarantee a robust performance over process-voltage-temperature (PVT) variations of the conventional frequency synthesizer, a frequency calibration scheme is proposed to automatically correct a frequency drift of quadrature injection locked oscillators. Implemented by a 65 nm CMOS process, the frequency synthesizer achieves a typical phase noise of -117 dBc/Hz @ 10 MHz offset from a carrier frequency of 61.56 GHz while consuming 72 mW from a 1.2 V supply. The calibration system consumes 65 mW additionally.

In this study, a C~K band frequency synthesizer used in broadband electronic warfare equipment was designed, developed, and the measurement results were presented. The structure of the designed frequency synthesizer generates a signal up to 6 GHz using only direct digital synthesizer(DDS) without a mixer or multiplier. For signals above 6 GHz frequency, the structure uses a multiplier. In addition, a variable sampling frequency structure and a DDS circuit were designed to improve signal quality by reducing spurious signals, harmonic signals, and phase noise. The developed frequency synthesizer has different signal quality performance depending on the use of the multiplier, and the C~G band has output power flatness ±1.7 dB, spurious signal less than −55 dBc, and phase noise less than −95 dBc/Hz (@1 kHz). The H~K band using multiplier has characteristics of output power flatness ±2.0 dB, spurious signal less than −35 dBc, and phase noise less than −80 dBc/Hz (@1 kHz). The results of this study confirmed the miniaturization of the signal generation module in the C~K band.

This paper presents system-level design and implementation of an ultra-wide tunable, high precision, fast locking, low phase noise, and low power portable fractional-N frequency synthesizer. The output frequency of the proposed design is ranged from 54 MHz to 6.8GHz. The VCO cores cover frequencies from 3.4GHz to 6.8GHz. The programmable output dividers allow generation of the lower frequencies. The frequency resolution of the implemented system is ±20 parts per million (ppm) over -40/85oC. The output power is tunable between -4dBm and +5dBm. The implemented system has a phase adjust feature that allows shifting of the output phase in relation to the reference oscillator ranged from 0° to 180°. It can generate a wide range, high precision, and linear frequency sweep. The sweep rate, frequency step, and frequency range are tunable. The new frequency tuning algorithm, named Yas algorithm, is proposed to improve frequency precision of the synthesizer. To demonstrate the efficiency of the Yas algorithm, the simulation result MATLAB and the experimental measurements are presented. The system consumes 300mA; therefore, it can be powered by Li-Ion battery. The output phase noise is -95.55 dBc/Hz at 1KHz offset from 3GHz. The experimental measurement results demonstrate that the implemented frequency synthesizer can be used for applications, such as oscillator of spectrum analyzer, automatic test equipment, FMCW radars, high-performance clock source for high speed data converter

Low phase noise frequency synthesizers are of paramount interest in many areas of micro-mm wave technology, encompassing for example advanced wireless communication, radar, radio-astronomy, and precision instrumentation. Although this broad research field is not bereft of methods for the generation of either low phase noise micro- or mm waves, no universal system applicable to low phase noise generation for micro and mm waves has yet been demonstrated. Here we propose a new photonic frequency discriminator based on a two wavelength delayed self-heterodyne interferometer which is compatible with such an objective. The photonic frequency discriminator can be a reference both for micro and mm waves to lower their phase noise. As a proof-of-concept, we demonstrate a low phase noise tunable OEO (6–18 GHz) and locking of a heterodyne beat between two cw lasers (10–400 GHz) with low relative phase noise. The required components for the photonic frequency discriminator are off-the-shelf and can be readily assembled. We believe this new type of photonic frequency discriminator will enable a new generation of universal precision tunable sources for the X, K, V, W and mm-bands and beyond.

The presence of laser phase noise (or frequency jitter) limits the resolution of a variety of interferometric sensors ranging from fiber optic acoustic sensors to gravitational wave detectors. At low frequencies, 0 to 100 kHz, the laser phase noise in semiconductor and diode pumped solid-state lasers is dominated by 1/f noise, the source of which is not well understood. We report on phase noise measurements for external cavity semiconductor lasers (ECSLs) utilizing a fiber Bragg grating in a compact butterfly package design produced by K2 Optronics. The results show that the phase noise is dominated by 1/f noise for low frequencies (10 to 100 kHz) transitioning to a white noise due to spontaneous emission for f > 100 kHz. We observed a factor of 40 improvement in the magnitude of the 1/f phase noise as compared to previously published results for a Hitachi HLP 1400 830 nm diode laser. The magnitude of the low frequency phase noise ranges from 100 to 10 microradians per meter per root Hz for frequencies ranging from 10 Hz to 2 kHz. These results are within a factor of 10 for phase noise measurements of the more expensive Lightwave Electronics Nd:YAG laser and a variety of Er-doped fiber lasers in this frequency range. For nominally similar ECSLs, experimental results indicate that the phase noise increases for lasers with larger leakage currents. Linewidth measurement results showed a Schawlow-Townes inverse power dependence for output powers up to 33 mWatts with the observed onset of a linewidth floor of 30 kHz. The RIN of the ECSLs varied from -120 to -155 dB Vrms per root Hz for frequencies ranging from 10 to 500 kHz. These RIN results are roughly equal to those observed for the Nd:YAG laser for frequencies less that 100 kHz. In summary, such low phase noise and RIN results make such ECSLs suitable for all but the most sensitive fiber optic sensing applications where the frequency range of interest is below 1 MHz.

The phase noise spectrum of a single loop frequency synthesizer for S-band, which can be utilized in broadcasting terminals, was predicted based on the analyses for phase noise contributions of noise sources. The proposed phase noise model in this paper more accurately predicts the phase noise spectrum of a frequency synthesizer. To accurately model the phase noise contributions of noise sources in the frequency synthesizer, the phase noise sources were analyzed via modeling of the frequency divider and phase noise components using Leeson model for the reference signal source and VCO. The phase noise transfer functions to VCO from noise sources were analyzed by superposition theory and linear operation of the phase-locked loop. The frequency synthesizers were fabricated and the phase noise prediction model was evaluated by measured data and prediction data.