A 90° phase-shift DLL with closed-loop DCC for high-speed mobile DRAM interface

This paper presents a wide frequency range CDR circuit for second generation AiPi+ intra-panel interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with conventional AiPi+. The DLL-based CDR architecture is adopted to generate multi-phase clocks. We propose a simple scheme for a frequency detector (FD) to overcome the limited frequency range and false lock problem of a conventional delay-locked loop (DLL) to reduce the complexity. In addition, a duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatches between rising and falling time of delay cells in the VCDL. Also, the proposed simple DLL architecture comprised of frequency and phase detectors has better process-portability. The proposed CDR is implemented in 0.18 μm technology and the active die area is 660 × 250 μm. The implemented DLL covers a frequency range from 62 to 128 MHz, which is limited only by the characteristics of the delay cell. The peak-to-peak jitter is less than 13 ps when the input frequency is 128 MHz, and the power consumption of the CDR except the input buffer, equalizer, and de-serializer is 5.94 mW from the supply voltage of 1.8 V.

This paper presents a fast locking duty cycle corrector (DCC) with high accuracy for mobile memory. The DCC has a low pass filter to convert detected values by duty cycle detector (DCD) into offset voltages and transmit the voltages to duty cycle adjuster (DCA) to adjust common mode voltages. The low pass filter has a tradeoff between correction time and accuracy depending on the capacitor value. The dual loop low pass filter (DLLPF) has been proposed for high accuracy and fast correction time. The locking time is 1.89 times faster and the fluctuation is 9.21 times lower compared to conventional low pass filter. The circuit is implemented in CMOS 0.18-µm technology using 1.8-V supply. The output duty cycle is corrected to 50±1% over the input duty cycle range of 20-80% for 1.6GHz.

A fast-locked all-digital delay-locked loop (DLL) with 50% output duty cycle is presented. A delay line using TSPC DFFs is re-used for the DLL and a time-to-digital converter. It results in a small-area and fast-locked DLL. The proposed DLL generates the output clock with 50% duty cycle in 4 cycles This DLL has been fabricated in a 0.18 um process. The core area is 350 um times105 um. The measured input frequency range is from 300 MHz to 500 MHz with input duty cycle of 40%~60%.

An algorithm is proposed for extraction of the unknown phase shift steps and correction of the phase shift error in partially coherent illuminated phase-shifting digital holography. The mean contrast of noise (MCN) of the reconstructed amplitude image is developed to evaluate the noise level resulting from phase shift error. Actual phase shift steps are first extracted by minimizing the MCN. Then the extracted actual phase shift steps are used to retrieve the original object wave without phase shift error. The validity of the proposed method is verified by simulations, and then implemented in partially coherent illuminated phase-shifting digital holography where a spatial light modulator with unknown phase modulation characteristic is used as the phase shifter. The results demonstrated that the actual phase shift steps can be extracted and the phase shift error is corrected effectively.

A high linear digital-to-phase converter (DPC) with 7-bit resolution is presented in this paper. The DPC consists of duty cycle corrector (DCC), delay-locked loop (DLL) and phase interpolator (PI). The interpolation is analyzed in detail, describing that reducing phase interval can improve linearity. Furthermore, nonlinear weighting technology is employed to suppress the systematic phase error. The DPC is implemented in standard 40nm CMOS technology and consumes 7.5mA in a 1.1-V supply with a DNL less than 13.2%.

Phase-shifting interferometry with a genetic algorithm is proposed. The correction of unknown phase-shifting error is an important task in general phase-shifting interferometry. Since phase-shifting errors generate twin image noise in a reconstructed image, we can reduce the phase-shifting errors indirectly by trying to eliminate the twin-image noise in the reconstructed image. By Zernike polynomial expansion, the reconstructed image is represented as the evenness and oddness, where the ratio of the evenness and oddness is a measure of the amount of the twin image noise. We employ the genetic algorithm for finding the fittest phase shifts of interferograms by reducing the evenness of the reconstructed image, which leads to reduction of phase-shifting errors. This phase-shifting interferometry with a genetic algorithm is confirmed experimentally.

The phase shift interferometer can be used to detect the wavefront phase of optical system and the piezoelectric transducer is widely used as a phase shifter in phase shift interferometer. However, the displacement of piezoelectric transducer presents hysteresis nonlinearity. Hence, when the equal-step phase shift algorithm (e.g. the Schwider-Hariharan phase-shifting algorithm which obtains five images and sets the phase-shifting between images to 90 degrees) is used in the phase shift interferometer to calculate the wavefront phase, the nonlinearity of piezoelectric transducer will introduce error to the 90 degrees phase-shifting between images. Then the calculated wavefront phase will contain the error. Hence, it is necessary to propose a method to diminish the phase error. The method by choosing an optimized phase-shifting algorithm has been used to mitigate the phase error. However, the method does not directly focus on piezoelectric transducer itself. In the paper, we propose a method by compensating for the hysteresis nonlinearity displacement of piezoelectric transducer to mitigate the phase error. We analyze the relationship between the nonlinearity displacement of piezoelectric transducer and phase shift error and establish the error models to analyze the relationship between the phase shift error and phase error. Furtherly, we propose the Proportion Integration Differentiation (PID) closed-loop feedback control method to compensate for the hysteresis nonlinearity displacement of piezoelectric transducer. The results indicate that, with compensated, the maximum tracking error is reduced from 18.89 % to 5.5 %. And in the ascending stage, the PV error and RMS error with compensated are less 12.35nm and 4.34nm than the PV error and RMS error without compensated. In the descending stage, the PV error and RMS error with compensated are less 19.15nm and 6.76nm than the PV error and RMS error without compensated. Hence, the proposed compensation method can improve the detection accuracy of the phase shift interferometer.

This paper presents a register controlled delay lock loop (RCDLL) with a time-to-digital converter (TDC) and a new fine delay line (FDL) scheme. The architecture of the proposed DLL uses a time-to-digital converter (TDC), a digital-to-time converter (DTC) scheme for short length of coarse delay line (CDL), and a open loop duty cycle corrector (DCC). While the conventional DLL has two feedback loops, the DLL with an open loop DCC has only one loop. So, it occupies a small area compared to the conventional one. Moreover, new FDL scheme is proposed which is capable of seamless boundary switching with a fixed delay step. HSPICE simulation results are based with ANAM 0.18/spl mu/m 1P6M CMOS process with 1.5V power supply voltage. Upon the simulation results, the proposed DLL operates correctly from 200MHz to 800MHz. The power consumption is less than 24mW at 800MHz. The active area of the design is 0.178mm/sub 2/.

Jitter is one of the most important parameters in design of delay locked loop (DLL) based frequency synthesizer. In this paper noise and mismatches of conventional delay cells which are mainly used in the DLLs architecture are introduced completely. First, time domain equations related to noise and mismatches of conventional delay cells are reported. Then, these equations are used to calculate jitter of DLL due to mismatch and noise of delay cells. At last closed form equations are obtained which can be used in the designing of low jitter DLLs. To validate these equations, a conventional DLL is designed in TSMC 0.18um CMOS Technology.

In this paper, an improved high resolution CMOS timing generator using array of digital delay lock loops is presented. The timing generator is implemented as an array of delay locked loops. This architecture enables a timing generator with sub gate delay resolution to be implemented. The proposed Delay Lock Loops use novel start controlled Dual Phase and frequency Detector along with a charge pump where the injected charge approaches zero as the loop approaches lock on the leading edge and the trailing edge of an input clock reference. The delay lock loop locks to both the leading and trailing clock edges as the start controlled dual phase and frequency detector along with charge pump convert the phase difference into voltage, which greatly reduces the timing jitter. In the start controlled dual phase and frequency detector, the start-controlled circuit is used to provide a precise output without the locking problem. The results show that the total delay time between the input and the output of the DLL (Delay Lock Loop) is one clock cycle and all of the delay cells provide precise output without false locking or harmonic locking. Test results show a timing jitter of less than 5 pS for the DLL circuit and has very low phase sensitivity errors. The timing generator implemented as an array of delay locked loops has exponentially reduced the locking time as well avoids false locking or harmonic locking. An experimental proto type was simulated using 0.35µ technology with a supply voltage of 3.3V.

An analogue synchronous mirror delay with duty cycle correction scheme (ASMDCC), to improve the data transmission performance between DRAM and system, is proposed. The ASMDCC achieves duty cycle correction and clock synchronisation at once within two clock cycles, by using a half value current source. The simulation results show the duty cycle of the internal clock is stabilised with less than ±100 ps deviation from 50% for the wide duty cycle range.

A phase shift selection method is proposed to design algorithms immune against phase shift errors in two-step generalized phase-shifting interferometry. A general formula for wavefront reconstruction error is derived, and its specific expressions for two common errors are also given. Calculation results suggest that the proper range of phase shift for general application is about from 0.5 to 2.0 rad for both the fixed and linear phase shift errors. Computer simulations have demonstrated the effectiveness of this phase shift selection method by decreasing the wave reconstruction errors to one-fifth.

Phase-shifting shadow moire is an efficient technique for three-dimensional (3-D) shape measurement, but the technique is always suffered from the error of phase shifter. A three-frame random phase-shifting algorithm is proposed to relax the requirements of repeatability and accuracy of the phase shifter in a shadow moire system. The proposed method can act as a bridge between the three phase-shifting analysis methods and two-shot phase-shifting methods. The value of introduced arbitrary and unknown phase shift can be calculated by a determinate formula. The algorithm has the advantages of being free from the disturbance of background elimination and less computation. In addition, the proposed method is immune to nonsinusoidal fringe patterns and can be implemented easily in many applications. Both simulation and optical experimental results verify the feasibility of this method.

Phase-shifting interferometry has many advantages, and the phase shifting nature of the Liquid Crystal Point Diffraction Interferometer (LCPDI) promises to provide significant improvement over other current OMEGA wavefront sensors. However, while phase-shifting capabilities improve its accuracy as an interferometer, phase-shifting itself introduces errors. Phase-shifting algorithms are designed to eliminate certain types of phase-shift errors, and it is important to chose an algorithm that is best suited for use with the LCPDI. Using polarization microscopy, the authors have observed a correlation between LC alignment around the microsphere and fringe behavior. After designing a procedure to compare phase-shifting algorithms, they were able to predict the accuracy of two particular algorithms through computer modeling of device-specific phase shift-errors.

A wide range, low jitter Duty Cycle Corrector (DCC) based on continuous-time integrator is proposed. It introduces little added jitter in the sampling edge, which make it good candidate for pipelined ADC application. The circuit is implemented in CMOS 0.35µm 2P4M Mixed Signal process. The experimental results show the circuit can work for a wide frequency range from 500kHz to 280MHz, with a correction error within 50%±1% under 200MHz, and the acceptable duty cycle can be as wide as 1-99% for low frequency inputs.