- https://doi.org/10.1007/978-3-319-73317-3_3
A Cache Consistency Protocol with Improved Architecture
- Jan 1, 2018
- Lecture notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering
- Qiao Tian +3 more
Abstract
The effective cache consistency protocol plays an important role in improving the processor performance. This paper designed an improved architecture of consistency protocol for multi-core environment, adding the D-Cache virtual bus to achieve the point-to-point consistency transaction transmission which avoided the bus idle phenomenon caused by the polling query method that the broadcast consistency transaction must be observed. The experimental results show that the architecture can improve the bus utilization.
- # Cache Consistency Protocol
- # Consistency Protocol
- # Architecture Of Protocol
- # Virtual Bus
- # Cache Consistency
- # Bus Utilization
- # Multi-core Environment
- # Effective Cache
- # Query Method
- # Processor Performance
