A compact charge-based model to study the nanoscale undoped double gate MOSFETs for nanoelectronic circuit design using genetic algorithms

Compact Modeling of Physical Mechanisms Present in the Weak Breakdown Regime of Advanced Si and SiGe Bipolar Transistors

This paper presents the feasibility of formalizing a compact modeling methodology for environmentally induced radiation effects, and of implementing that methodology into the Paragon compact modeling tool. For demonstration purposes, the paper focuses on two specific radiation effects implemented in a MOSFET device model. These two effects were chosen in order to illustrate two differing forms of model development. The first form takes existing device models and modifies the equations and/or variables already existing within that model to achieve the required results (behavioral modification). The second form adds completely new equations and variables to existing device models (behavioral augmentation). The MOSFET (1) threshold voltage shift due to total ionizing dosage (TID) and (2) leakage current increase due to TID, are two major device effects that fulfill both of these requirements. Voltage shift and leakage current are critical design issues in rad-hard electronics and space environments. The threshold voltage shift effects are implemented through the modification of device model equations, while leakage current increases are implemented with added behavioral macros to the model topology, thus fulfilling the second requirement. The use of the modified compact MOSFET model is illustrated in the simulation of an op-amp based filter. Gain and frequency shifts can be observed and compared as the circuit absorbs differing amounts of TID.

We present a 2D physics based compact model of the double gate (DG) and the gate‐all‐around (GAA) MOSFET, with emphasis on short‐channel devices of nano‐scale dimensions. The compact model is based on a preprocessing routine based on a self‐consistent framework for electrostatics modeling. For sub‐threshold conditions, we assume that the device body is dominated by the solution of the 2D Laplace electrostatics. This assumption is based on the fact that the field strength at the gates emerging from the mobile charge carriers and the doping are much weaker than the fields related to the capacitive coupling between the contacts and the gates. Therefore, we neglect the body charge term in Poisson's equation, converting it to a Laplace equation. Near threshold, the influence of the electronic charge on the electrostatics is taken into account in the framework model in a precise, self‐consistent manner by combining suitable model expressions with the 2D Poisson's equation in the device body. To this end, we consider the self‐consistent potential distributions along the two symmetry axis. Suitable modeling expressions are applied, whose parameters are determined from the boundary conditions and by enforcing self‐consistency using Poisson's equation. The framework and the compact model give excellent results when compared with numerical simulations. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

This paper presents a novel compact modeling approach to consider the effect of trap-assisted tunneling (TAT) in the calculations of the tunneling current in tunnel field-effect transistors (TFETs). The closed-form and physics-based model equations are implemented in the hardware description language Verilog-A and thus extend an existing model for the B2B tunneling current calculation in double-gate (DG) TFETs.In order to verify the modeling approach, simulation results are compared to TCAD Sentaurus simulations. The compact model shows a good fit in the current transfer curves for various drain-source voltages, trap densities, drain doping concentrations and different source materials. The current output curve and the output conductance stay also in good agreement with TCAD data. In the next step, the compact model is verified with the help of measurements of fabricated complementary TFET devices. During the verification process, limitations and advantages of the modeling approach are analyzed and discussed. The influence of TAT on a fabricated single-stage TFET inverter is investigated in a last verification step, whereby the numerical stability and flexibility of the model is demonstrated.

A compact quantum correction model for a symmetric double gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) is investigated. The compact quantum correction model is proposed from the concepts of the threshold voltage shift (ΔVTHQM) and the gate capacitance (Cg) degradation. First of all, ΔVTHQM induced by quantum mechanical (QM) effects is modeled. The Cg degradation is then modeled by introducing the inversion layer centroid. With ΔVTHQM and the Cg degradation, the QM effects are implemented in previously reported classical model and a comparison between the proposed quantum correction model and numerical simulation results is presented. Based on the results, the proposed quantum correction model can be applicable to the compact model of DG MOSFET.

A compact subthreshold characteristics model for short channel fully-depleted double-gate (DG) junctionless field effect transistors (JL FETs) which is based on an approximated solution of 2 dimensional Poisson’s equation has been proposed. The derivation details are introduced and the model’s accuracy has been verified by comparison with both previous models and the TCAD simulations’ results which proves that the subthreshold characteristics such as channel potential distribution, subthrethold drain-to-source current, subthreshold slope, drain-induced-barrier-lowering and threshold voltage can be accurately predicted by our proposed compact model.

A generic double-gate (DG) MOSFET follows a generalized voltage equation from the first integral of Poisson equation and Gauss' law applied at the two gates, which is implicit and, in general, non-integrable when the silicon film is doped. Only DG with undoped body can be solved with implicit surface-potential solutions, or approximate surface-potential solutions for doped symmetric-DG (s-DG) structures. The most challenging task in DG compact modeling is the surface-potential solutions for the generic asymmetric-DG (a-DG) doped-body device: scalable over oxide thickness (from DG to SOI), body thickness and doping (from ultra-thin-body/fully-depleted to bulk-like/partially-depleted), and gate bias (from s-DG and common-gate a-DG to independent-gate a-DG). Once it is conquered, the model will be able to cover different structures and operations with seamless transitions. Another challenge is extension of a DG model to multiple-gate (MG) such as tri-gate (TG) and silicon nanowire (SiNW) devices, or a unified model that encompasses all different configurations. In this paper, we present solution methods towards such a unified MOS compact model based on the unified regional modeling (URM) approach.

Optimal costing of overhead power transmission lines using genetic algorithms

In recent years, high‐specification products such as high brightness, wide temperature range, narrow bezel, and high resolution have been a major trend in the display market. However, the enhancement of specifications often comes with extreme design challenges, posing significant challenges to product reliability. This paper establishes a compact model for amorphous silicon (a‐Si) device aging and aging simulation process to predict the degree of circuit performance degradation of amorphous silicon liquid crystal displays under various aging conditions (including photo‐thermal and their combined conditions). The accuracy of this compact model reaches 91.7%. When using this model for circuit simulation, it can reflect the waveform and device decay, and the circuit degradation results are essentially consistent with the actual product performance. This can quickly and effectively optimize the design and provide a reference for designers to assess product reliability in the early stages of product design.

A problem nowadays tissue engineers encounter in developing sizable tissue implants is the nonuniform spread of cells and/or extracellular matrices. Research shows such a nutrients transport restriction may be improved by employing hydrodynamic culture systems. We propose a compact model for the simulation of cell growth in a porous construct under direct perfusion. Unlike the previous model proposed in the literature, which composes a cellular scaffold sandwiched between two culture media layers, the current model includes only the scaffold layer to simplify the mathematical and computational complex. Results show the present single-layer model can predict cell spreads and the nutrient and metabolic waste distribution as accurately as does the three-layer model. Only if the hydrodynamic aspects such as the pressure and viscous stress are prominent to know, should the more sophisticated analyses with the three-layer model be employed. The compact model provides comparable investigations for the tissue-engineering construct developments.

This paper presents efficiency optimization of switched reluctance motor based on genetic algorithm optimization technique. Switched reluctance motor (SRM) is considered for various applications due to its simple and robust construction. It is very essential to improve efficiency of switched reluctance motor. In this paper, optimization of 8/6 switched reluctance motor is achieved by using genetic algorithm with efficiency as its objective function. The objective of the paper is to identify the best switched reluctance motor design that provides better efficiency to satisfy the unique requirements of various applications. Using finite element analysis, a design validation of motor and characterization was made. It is analyzed that analytical results and simulation results are very close which establishes correctness of designs. The optimization result shows that the newly developed SRM design achieved better efficiency. The efficiency is increased from 82.75 % to 86.19 % with minor increase in weight. Improvement in efficiency can lead to lower energy usage, longer motor life span, and better performance.

In this work, we performed a quantum reactive study using a new potential energy surface (PES) fitted to the Na + HF→NaF + H reaction. The new PES was obtained using the genetic algorithm optimization technique (GAOT). We calculated the reactive probabilities (RP) of the Na + HF system using the new PES. The GAOT RP are compared with the obtained RP using two other PES found to the Na + HF system: Bond Order 5 (BO5) and the generalized simulated annealing (GSA) PES. We found that the GAOT RP are in excellent agreement with the GSA and BO5 RP. It should be point out that the BO5 RP are considered the benchmark of literature. Therefore, the GAOT is shown to be an appropriate method to fit PES of reactive systems. © 2008 Wiley Periodicals, Inc. Int J Quantum Chem, 2008

Proper diagnosis of breast cancer is one of the main issues in a medical sector. The neural network could overcome the issue, but weak in determining parameter value, therefore it requires optimization. A genetic algorithm is one of the optimization methods, due to that matter, attribute parameter value of neural network will be optimized by using Genetic Algorithm to acquire the best predictor attributes. Genetic-based Neural Network algorithm has higher accuracy compared to the application of Neural Network algorithm alone. This notion is proven through the increasing rate of accuracy value for Neural Network algorithm which amounted to 96.57 % and 97.24 % for Genetic-Based Neural Network Algorithm as well as the decreasing rate of error classification of Neural Network algorithm model from 3.43 % rate to 2.86 % due to the application of Genetic-Based Neural Network Algorithm. Therefore, it can be concluded that the application of the optimization technique of Genetic Algorithm can enhance the accuracy value and decrease the error value of the Neural Network algorithm on breast cancer classification.

Compact models of semiconductor devices play a crucial role in design and analysis of large circuits. This paper presents a qualitative study of diode compact models including temperature dependency and reverse recovery phenomenon. The comprehensive behaviour of p-n junction diode is captured using Verilog-A language which is compatible to standard SPICE simulators. In this work, three types of diode models have been investigated based on temperature scale. Similar to SPICE compact models, a set of tuneable parameters are defined and presented for each type. In addition, an extensive study of reverse recovery has been done to determine the magnitude of reverse current and to evaluate model parameters like charge storage time and transition time based on input switching and temperature. Simulation results show that the developed model in this work is compatible like standard compact model scalable with area, temperature and intrinsic carrier concentration.

In this work, we investigate the electrical properties of the Double-Gate MOSFET (DG-MOSFET), which turn out to be very promising for device miniaturization below 0.1 -4im. A compact model which accounts for charge quantization within the channel, Fermi statistics, and nonstatic effects in the transport model is worked out. The main results of this investigation are: 1) the ideality factor in subthreshold is equal to unity, i.e., the slope of the turn-on characteristic is 60 mV/decade at room temperature; 2) the drain-induced barrier lowering is minimized by the shielding effect of the double gate, which allows us to reduce the channel length below 30 nm; and 3) the device transconductance per unit width is maximized by the combination of the double gate and by a strong velocity overshoot which occurs in response to the sudden variation of the electric field at the source end of the channel, and which can be further strengthened near the drain in view of the short device length. As a result, a sustained electron velocity of nearly twice the saturation velocity is achievable. The above results prove that the potential performance advantages of the double-gate device architecture may be worth the development effort. ) ©1999 IEEE.