A comparison of five different multiprocessor SoC bus architectures

A split shared-bus architecture with multiple simultaneous bus accesses is proposed. Compared to traditional bus architectures, the performance of proposed architecture is higher because of the ability to deliver multiple bus transactions in one bus cycle. We also propose an implementation of the arbiter, which not only detects and grants multiple compatible bus transactions, but also controls splitters properly to establish the communication paths for those transactions. Experimental results show that the bus architecture can have up to 2.3 times improvement in the effective bandwidth and up to 5 times reduction in the communication latency. Moreover, the arbiter implementation has reasonable area and timing cost, making it suitable for high performance SoC applications.

System-on-a-chip (SoC) is now a trend in digital design because it gives a lot of advantages over discrete electronic based product such as higher speed, lower power consumption, smaller size, lower cost etc. Reconfigurable platforms such as FPGA, CPLD, and PLD are now being used for designing and implementing SoC due to their low cost, high capacity and tremendous speed. In this project single chip Orthogonal Frequency Division Multiplexing (OFDM) transmitter and receiver have been designed using Verilog HDL. OFDM is a multi carrier modulation technique used in the various digital communication systems like 3G GSM, WiMAX and LTE etc. The main advantage of this transmission technique is its robustness to channel fading in wireless communication environment. There are many applications of OFDM in communication such as digital audio broadcasting, Asynchronous Digital Subscriber Line (ADSL) and High bit-rate Digital Subscriber Line (HDSL) systems. In OFDM, two algorithms digital signal processing algorithm Fast Fourier transform (FFT) and Inverse Fast Fourier Transform (IFFT) are mainly involved. The 8-point IFFT/FFT Decimation-In-Frequency (DIF) with radix-2 algorithm has been analyzed and incorporated in the design. The design has been simulated on the FPGA platform with Altera's Quartus II simulator. Simulation results show that each of the modules of the proposed OFDM is working as desired. The test output achieved from the simulation result of the OFDM has been verified with that of the MATLAB output.

The SoC (System on Chip) uses AMBA (Advanced Microcontroller Bus Architecture) as an on chip bus. APB (Advanced Peripheral Bus) is one of the components of the AMBA bus architecture. APB is low bandwidth and low performance bus used to connect the peripherals like UART, Keypad, Timer and other peripheral devices to the bus architecture. This paper introduces the AMBA APB bus architecture design. The design is created using the verilog HDL and is tested by a System verilog test- bench. This design is verified using SV. A reuse based methodology for SoC design has become essential in order to meet these challenges. The work embodied in this paper presents the design of APB Protocol and the Verification of slave APB Protocol. Coverage analysis is a vital part of the verification process; it gives idea that to what degree the source code of the DUT has been tested. The functional coverage analysis increases the verification efficiency enabling the verification engineer to isolate the areas of untested function. The design and verification IP is built by developing verification components using Verilog and System Verilog respectfully with relevant tools such as Questasim and Cadence, which provides the suitable building blocks to design the test environment.

As per Moore’s law, the number of transistors doubles every eighteen months this advance in technology grown to the level where SOC (System On Chip) became evident of this growth. This growth does not stop here further it turned into Network On Chip. But the bus technology which supported System On Chip cannot be used with Network On Chip Technology. Bus architecture when combined with NOC it was suffering from several issues like poor scalability, limited bandwidth and low resource utilization. To address these issues, routing algorithms and switching techniques are used. In this paper two such algorithms are compared. One is adaptive Odd even (OE) routing algorithms and another is Extended XY algorithm. It’s been noticed that extended XY gives better performance in turns of Hop count and all the minimum paths are utilized in Extended XY routing algorithm unlike in OE few turns are prohibited.KeywordsNOC (Network on Chip)SOC (System on Chip)OE (Odd Even)XYExtended XY

In the present era the increased complexity of design decreases the design cycle and reduces the cost. Efficient power consumption has led to the arrival of methodology of system-on-chip (SoC) in the semiconductor industry. A SoC usually contains reusable IPs, memory elements, bus architecture, that is for interfacing IPs, clock circuits and mixed signal blocks SRAM, that is embedded processors or controllers, and other components on SoC, programmable blocks, that is FPGA, and so on. The functionality of SoC can be easily improved by integrating more intellectual property (IP) components within it. A number of SoCs is integrated to form more complex system. Though the reuse of IPs on SoC has increased the hazard of misuse of IPs to the third-party entries, but it still plays an integral part of SOCs [1]. In silicon, IPP (industries IP protection) technique has been implemented in design flow of VLSI and has been extended to security considerations for SoC design methodology. In this paper the authors created IPs for Ethernet and HDMI using Xilinx Vivado 18.2, which is built for internet of things (IoT) application.

It is well known that Orthogonal Frequency Division Multiplexing (OFDM) systems suffer from intercarrier interference (ICI) in mobile environment due to loss of orthogonality among subcarriers caused by Doppler shifts. There exist many ICI mitigation techniques in the literature to improve the performance of OFDM systems. However, most of the existing ICI mitigation techniques assume the OFDM transmission bandwidth is narrow enough that the frequency offsets on all subcarriers are identical. In a wideband OFDM transmission or a non-contiguous OFDM spanning over large bandwidth, the Doppler shifts on different subcarriers are different, especially in high speed aerial vehicle communication systems. In this paper, we analyze the wideband OFDM system in high mobility environment where the frequency offsets vary from subcarrier to subcarrier. We then propose a novel ICI cancellation scheme to eliminate the ICI effect and offer the wideband OFDM system significantly improved BER performance. Simulation results in AWGN channel and multipath fading channel confirm the effectiveness of the proposed scheme in the presence of frequency offset and time variations in the channel, offering the best BER performance available which matches the BER performance of wideband OFDM system without ICI. To our knowledge, this paper is the first to address the ICI problem of varying frequency offsets across subcarriers in wideband OFDM system.

기존에 사용되는 대부분의 SoC는 공유버스 구조를 가지고 있어, 병목현상이 발생하는 문제점을 가지고 있다. 이러한 문제점은 SoC의 내부의 IP 수가 많을수록, 전체적인 SoC의 성능을 저하시키게 되어, CPU 자체의 속도보다는 전체적인 통신 분배에 의해 SoC의 성능이 좌우 된다. 본 논문에서는 공유버스의 단점인 병목현상을 줄이고 SoC의 성능을 향상시키기 위해 크로스바 스위치버스 구조를 제안한다. 크로스바 스위치 버스는 마스터 모률 8개, 슬레이브 모듈 16개까지 연결이 가능하며, 다중 버스 채널구조로 되어 있어 병렬통신이 가능하다. 또한 각 16개의 슬레이브 인터페이스마다 우선순위 정보가 저장된 아비터가 내장되어 하나의 마스터가 슬레이브를 독점하는 것을 방지하는 것과 동시에 효율적인 통신을 지원한다. OpenRISC 프로세서, VGA/LCD 제어기, AC97 제어기, 디버그 인터페이스, 메모리 인터페이스로 구성되는 SoC 플랫폼의 WISHBONE 온칩 공유버스 구조와 크로스바 스위치 버스구조의 성능을 비교한 결과, 기존의 공유버스보다 26.58%의 성능이 향상되었다. Most of the existing SoCs have shared bus architecture which always has a bottleneck state. The more IPs are in an SOC, the less performance it is of the SOC, Therefore, its performance is effected by the entire communication rather than CPU speed. In this paper, we propose cross-bar switch bus architecture for the reduction of the bottleneck state and the improvement of the performance. The cross-bar switch bus supports up to 8 masters and 16 slaves and parallel communication with architecture of multiple channel bus. Each slave has an arbiter which stores priority information about masters. So, it prevents only one master occupying one slave and supports efficient communication. We compared WISHBONE on-chip shared bus architecture with crossbar switch bus architecture of the SOC platform, which consists of an OpenRISC processor, a VGA/LCD controller, an AC97 controller, a debug interface, a memory interface, and the performance improved by 26.58% than the previous shared bus.

A tri‐layer bus system‐on‐chip (SoC) and a butterfly‐path accelerator are used to enhance system‐level performance in a sequential minimal optimisation learning core. The tri‐layer bus architecture is used to obtain an adequate transfer rate. The butterfly‐path accelerator also uses symmetrical access to resolve bottlenecks during linear prediction cepstral coefficients extraction. This novel design increases speed and flexibility without substantially increasing area. For implementation in chip manufacturing, the SoC is synthesised, placed and routed using the TSMC 90 nm technology library. The die size is 2.09 mm × 2.09 mm, and the power consumption is 8.9 mW. Compared with the non‐butterfly‐path design, the simulation results show that the proposed architecture provides a 2.4‐fold speed increase. In addition, clock down‐sampling and voltage scaling reduce the power consumed by the proposed chip by a factor of 8.5. The experimental results confirm the improved speed and power that are provided by the proposed architecture and methods.

High peak to average power ratio (PAPR) is a serious drawback for orthogonal frequency division multiplexing (OFDM) system as it reduces the efficiency of high-power amplifiers commonly used in the transmitter and causes spectral spillage. OFDM transmissions are also sensitive to frequency selective fading channels which can severely attenuate certain parts of the signal making it much more vulnerable to additive noise. This paper proposes an effective precoding technique with the dual ability to both reduce PAPR and condition the OFDM signal against frequency selective fading channels. It will be demonstrated that by advisedly creating diversity among the subcarriers of one OFDM symbol, and exploiting it with a dirty- paper-coding (DPC) approach, excellent bit-error-rate (BER) performance is achieved without reducing transmission rate. Low PAPR factor can also be obtained through a proper selection of diversity matrix that distributes the power of each modulated symbol over the OFDM block. Simulation results show that the proposed technique has not only better BER performance than the ordinary channel inversion but also similar PAPR reduction ability to the selective mapping (SLM) technique.

We investigate a novel dispersion compensating technique in double sideband (DSB) modulated and directed-detected (DD) passive optical network (PON) systems using super-Nyquist image induced aliasing. We show that diversity is introduced to the higher frequency components by deliberate aliasing using the super-Nyquist images. We then propose to use fractional sampling and per-subcarrier maximum ratio combining (MRC) to harvest this diversity. We evaluate the performance of conventional orthogonal frequency division multiplexing (OFDM) signals along with discrete Fourier transform spread (DFT-S) OFDM and code-division multiplexing OFDM (CDM-OFDM) signals using the proposed scheme. The results show that the DFT-S OFDM signal has the best performance due to spectrum spreading and its superior peak-to-average power ratio (PAPR). By using the proposed scheme, the reach of a 10-GHz bandwidth QPSK modulated OFDM-PON can be extended to around 90 km. We also experimentally show that the achievable data rate of the OFDM signals can be effectively increased using the proposed scheme when adaptive bit loading is applied, depending on the transmission distance. A 10.5% and 5.2% increase in the achievable bit rate can be obtained for DSB modulated OFDM-PONs in 48.3-km and 83.2-km standard single mode fiber (SSMF) transmission cases, respectively, without any modification on the transmitter. A 40-Gb/s OFDM transmission over 83.2-km SSMF is successfully demonstrated.

Orthogonal frequency division multiplexing (OFDM) has been adopted in various wireless communication standards to exploit its high spectral efficiency and robustness against multipath fading channels. Along with the potential benefits of OFDM transmissions, a stringent requirement on orthogonality among subcarriers makes OFDM highly susceptible to synchronization errors, i.e., time and frequency offsets. Addressing the carrier frequency offset (CFO) estimation problem, the paper proposes a pilot-aided CFO estimation scheme for both coarse and fine carrier frequency synchronization in single-input single-output (SISO) OFDM receivers. By exploiting the maximum likelihood (ML) principle, the proposed ML-based CFO estimation algorithm functions properly over a wide range of CFO values and outperforms existing correlation-based schemes.

FFT(Fast Fourier Transform) 알고리즘에는 DIT(Decimation-In-Time)와 DIF(Decimation-In-Frequency)가 있다. DIF 알고리즘은 Radix-2/4/8 등의 다양한 종류와 그 구현 방법이 개발되어 사용되고 잇으나, DIT 알고리즘은 순차적인 출력을 낼 수 있는 장점이 있음에도 불구하고 다양한 알고리즘이 연구되지 못하였다. 이 논문에서는 새로운 DIT Radix-4 FFT의 나비연산기(butterfly) 구조를 제안하고 검증하였다. 제안 구조를 사용하여 64-point FFT 구조를 설계하고 Verilog로 코딩하여 구현함으로써 제안 구조의 효용성을 입증하였다. 48개의 곱셈기를 사용하여 합성하였으며 678만 게이트 수를 나타내었다. 따라서 제안된 DIT Radix-4 FFT 구조는 순차적인 FFT 출력을 필요로 하는 OFDM 통신용 SoC(System on a Chip)에 사용될 수 있을 것이다. Two basic FFT(Fast Fourier Transform) algorithms are the DIT(Decimation-In-Time) and the DIF (Decimation-In-Frequency). In spite of the advantage of the DIT algorithm is to generate a sequential output, various structures have not been made. In this paper, a new DIT Radix-4 FFT butterfly structure are proposed and implemented using Verilog coding. Through synthesis, it is shown that the 64-point FFT is implemented by 6.78 million gates. Since the proposed FFT structure has the advantage of a sequential output, it can be used in OFDM communication SoC(System on a Chip) which need a high speed FFT output.

In this paper, we propose a novel sidelobe suppression approach for cognitive radio systems employing orthogonal frequency division multiplexing (OFDM) transmission. OFDM is a promising solution for future overlay wireless access due to its high data rate and flexibility. However, OFDM and its variants employ sinc-type pulses in representing the symbols transmitted over all subcarriers during one time instant. Consequently, large sidelobes can occur that could potentially interfere with the signal transmissions of the neighboring legacy systems or with the transmissions of other rental users. To mitigate this source of interference, both cancellation carriers (CCs) and modulated filter banks (MFB) can be employed. In this paper, raised-cosine filter is chosen without loss of generality as the prototype filter for the modulated filter banks. The power spectrum density of the OFDM signal after employing different CC algorithms, different number of CCs and different parameters of raised-cosine filters, such as the roll off factor, are analyzed and compared. Simulation results show that this combination approach can achieve significant reduction for OFDM out-of-band radiation and the sidelobe can be suppressed down to −70 dBm.

Orthogonal Frequency Division Multiplexing (OFDM) transmissions are emerging as important modulation technique because of its capacity of ensuring high level robustness against interference. This paper presents a prototype of a high throughput and low complexity OFDM transceiver. OFDM is a modulation technique which is now widely used in various high speed mobile and wireless communication systems such as: fixed Wi-Fi system (IEEE 802.11a standard), mobile Wi-Fi system (IEEE 802.11b standard), fixed WiMAX system (IEEE 802.16a standard), and mobile WiMAX system (IEEE 802.16e standard). In this paper, the design and implementation of OFDM system will be illustrated. Moreover, the design and simulation results for some standards of OFDM using MATLAB will be observed as a practical system examples that uses OFDM as a modulation technique. All the proposed modules are designed using VHDL programming language. The transceiver is implemented on a Field-Programmable Gate Array (FPGA) through Xilinx System Generator for DSP. The proposed transceiver provides low processing latency. A rapid prototyping platform interfacing MATLAB with Xilinx kit is used in this development. Our experiments show that the proposed transceiver utilizes 68% of the slice LUTs and 55% of slice registers on Virtex-6 FPGA, operating at a maximum frequency of 112 MHz, which proof that our design have the lowest area over the previous related work presented before.

A novel encryption scheme using chaotic Zadoff-Chu matrix transform (ZCMT) precoding is proposed to improve both of the data security and performances in orthogonal frequency-division multiplexing (OFDM) transmission, where the security is significantly enhanced with a huge key space of ∼10400 provided by hyper digital chaos. The chaotic ZCMT matrix is generated with the reconfigurable parameters and row permutation of ZCMT matrix, both of which are predetermined by a hyper digital chaos. The OFDM data encryption using the chaotic ZCMT precoding effectively reduces the peak-to-average power ratio (PAPR) and consequently improves the OFDM transmission performance, if compared with the traditional OFDM transmission. The significant PAPR reduction is numerically analysed via the autocorrelation and the complementary cumulative distribution function (CCDF).