A Comprehensive Reliability Analysis Framework for NTC Caches: A System to Device Approach

Near-Threshold Computing (NTC), where the supply voltage is only slightly higher than the threshold voltage of transistors, is a promising approach to attain energy-efficient computing. Unfortunately, compared to the conventional Super-Threshold Computing (STC), NTC is more sensitive to process variations, which results in higher power consumption and lower frequencies than would otherwise be possible, and potentially a non-negligible fault rate. To help address variations at NTC at the architecture level, this paper presents the first microarchitectural model of process variations for NTC. The model, called VARIUS-NTV, extends the existing VARIUS variation model. Its key aspects include: (i) adopting a gate-delay model and an SRAM cell type that are tailored to NTC, (ii) modeling SRAM failure modes emerging at NTC, and (iii) accounting for the impact of leakage in SRAM models. We evaluate a simulated 11nm, 288-core tiled manycore at both NTC and STC. The results show higher frequency and power variations within the NTC chip. For example, the maximum difference in on-chip tile frequency is ≈2.3× at STC and ≈3.7× at NTC. We also validate our model against an experimental chip.

This paper proposes a novel low power 8T SRAM cell for write operation. In the proposed structure, two voltage sources VS1 and VS2 are connected with the bit line and the bit bar line, respectively. These voltage sources reduce the swing voltage and reduction in swing voltage causes the reduction in dynamic power dissipation of the proposed SRAM cell. Also, two different leakage power reduction techniques called upper self controllable voltage level (USVL) and lower self controllable voltage level (LSVL) have been proposed and applied individually and in combination with the proposed 8T SRAM for the reduction of leakage current. Both the leakage current and power dissipation results are compared with those of conventional 6T and 7T SRAM cells reported in different literatures. Static noise margin is also analysed during write operation for stability purpose. The proposed SRAM cell has lesser leakage current in comparison to conventional 6T SRAM cell and also dissipates the least amount of power and yields better stability in comparison to both 6T and 7T SRAM cells. The authors use 45 nm CMOS technology with 0.5 volt power supply for simulation purpose. Microwind 3.1 software is used for schematic design and simulation.

This paper presents a new 8T (8-transistor) SRAM cell layout mitigating multiple-bit upset (MBU) in a divided wordline structure. Because bitlines along unselected columns are not activated, the divided wordline structure eliminates a half-select problem and achieves low-power operation, which is often preferred for low-power / low-voltage applications. However, the conventional 8T SRAM with the divided wordline structure engenders MBUs because all bits in the same word are physically adjoining. Consequently, error correction coding (ECC) techniques are difficult to apply. This paper presents a new 8T cell layout pattern that separates internal latches in SRAM cells using both an n-well and a p-substrate. We investigated an SEU cross section of nMOS that is 3.5–4.5 times higher than that of pMOS. Using an iRoC TFIT simulator, we confirmed that the proposed 8T cell has better neutron-induced MBU tolerance. The MBU in the proposed 8T SRAM is improved by 90.70% and the MBU soft error rate (SER) is decreased to 3.46 FIT at 0.9 V when ECC is implemented. Additionally, we conducted Synopsys 3-D TCAD simulation, which indicates that the LET threshold (LETth) in single-event upset (SEU) is also improved by 66.47% in the proposed 8T SRAM by a common-mode effect.

In this paper analysis of noise margin and power dissipation of a novel low power proposed 8T SRAM cell has been reported. In the proposed structure two voltage sources are connected with the Bit line and the other connected with the Bit bar line are used in order to reduce voltage swings at the output nodes of bit and bit bar line during the write operation. Static noise margin values have been calculated at different transistor cell ratios and different transistor pull-up ratios. Similarly the power dissipations at different supply voltages, temperatures and bit line capacitances are calculated. Results of static noise margin and power dissipations are compared to those of conventional 6T and 11T SRAM cells. The proposed SRAM cell has better stability at different cell ratios and pull-up ratios in comparison to 6T and 11T SRAM cells. Power dissipation in the proposed SRAM cell is less at different supply voltages, temperatures and bit line capacitances in comparison to 6T and 11T SRAM cells. The simulation has been done in 350nm CMOS environment by using BSim4 model. Microwind 3.1 is used for schematic design.

For the first time through this paper, a Static Random Access Memory using 9T SRAM, 8T SRAM and 6T SRAM has been compared using N-curve and statistical analysis which demonstrated a multi-fold performance enhancement. In this paper, 9T SRAM cell with extra transistors compared to 8T SRAM and 6T SRAM cells, is giving the higher stability (SVNM, SINM, WTV, and WTI) as compare to conventional SRAM cells. The paper analysis the variety of parameters such as stability (SVNM, SINM, WTV, and WTI), area and leakage power consumption. A comparison based study of the Cell Ratio (CR), the Pull-up-ratio (PR) with SVNM has been shown. A statistical model has been developed displaying the power histogram during the write and read cycle for the 9T SRAM cell. The 9T SRAM cell shows a much better stability, less standby power consumption and higher area as compare to 6T and 8T SRAM cell counterparts. The design is based on the 90 nm CMOS process technology.

In this paper, a comparison has been drawn between 5 transistor (5T), 6T and 7T SRAM cells. All the cells have been designed using both single-threshold (conventional) and dual-threshold (dual-Vt) voltage techniques. Their respective delays and power consumption have been calculated at 180 nm and 65 nm CMOS technology. With technology scaling, power consumption decreases by 80% to 90%, with some increase in write time because of the utilization of high- Vt transistors in write critical path. The results show that the read delay of 7T SRAM cell is 9% lesser than 5T SRAM cell and 29% lesser than 6T SRAM cell due to the lower resistance of the read access delay path. While read power of 5T SRAM cell is reduced by 10% and 24% as compared to 7T SRAM, 6T SRAM cell respectively. The write speed, however, is degraded by 1% to 3% with the 7T and 5T SRAM cells as compared to the 6T SRAM cells due to the utilization of single ended architecture. While write power of 5T SRAM cell is reduced by up to 40% and 67% as compared to 7T SRAM, 6T SRAM cell respectively.

In this paper, a new asymmetric 6T (AS6T) SRAM cell is presented in a standard 90-nm CMOS technology employing separate bitline and wordline for read operation. Utilizing separate bitline and wordline during read operation decouples the other cell node from the bitline, hence, enhancing the read static noise margin (SNM) by almost 2 times as compared to the conventional 6T SRAM. The read SNM of 6T and AS6T SRAM cells during a read operation in 1.0 V supply is 85 mV and 159 mV, respectively. The mean μ of the hold SNM for both cells are well above 140 mV, however, the μ of the conventional 6T SRAM is larger than that of AS6T cell. The impact of process parameter variations on read and hold noise margin of the asymmetric 6T cell and the conventional 6T cell, considering various supply voltages, is investigated. The results demonstrate yield improvement, up to 99.5%, and indicate that the supply voltage can scale down to 0.45 V.

Low power cache memory in a system on chip is in high demand today. With the lowering of MOSFET’s channel length, low-power SRAM design has become a more challenging task. This paper presents differential 8T SRAM cell with minimum power utilization. The proposed cell has one pair of transmission gate as access switches. Due to use of TG instead of pass gate access transistor its write access time (TWA) is short. The low power consumption of the cell is due to stacking effect. This paper compares design metrics of the proposed cell with conventional 6T (CON6T) and ZIGZAG 8T (ZG8T) SRAM cells. The proposed 8T SRAM cell shows 1.15×/1.17× improvement in TWA as compared to CON6T/ZG8T at a penalty of 2.65×/2× in read access time (TRA). The proposed cell consumes 3.22× less hold power compared to both CON6T and ZG8T SRAM cells. And the proposed cell consumes 4.41× (4.44×) less write power as compared to CON6T (ZG8T) SRAM cell. Our proposed cell takes 1.37× lower chip area as compared to ZG8T cell at the expense of 1.49× higher area as compared to CON6T SRAM cell. The proposed cell also achieves 1.5×/3× higher stability during write operation as compared to CON6T/ZG8T SRAM cell, respectively. Read static margin of the proposed cell is same as CON6T but 3.2× lower than ZG8T SRAM cell.

The need for low-power SRAM results in many design challenges in deep submicron technology. In this paper, 6T, 7T and 8T SRAM cells designed in 65nm bulk CMOS technology in the subthreshold region have been compared on the basis of various Figures of Merit (FoMs). The 7T and 8T SRAM cells are able to work at 200mV with 8T exhibiting highest Read Static Noise Margin (RSNM), Hold Static Noise Margin (HSNM) and Write Noise Margin (WNM). All cells result in low leakage in the subthreshold region. Statistical Analysis has been carried out to examine the effect on RSNM due to on-die parametric fluctuations.

This paper investigates the static noise margin (SNM) of ultrathin-body (UTB) SOI SRAM 6T/8T cells operating in the subthreshold region using analytical solutions of Poisson's equation validated with TCAD simulations. An analytical framework to calculate the SNM for UTB SOI SRAMs operating in the subthreshold region is presented. Our results indicate that for improving both read SNM (RSNM) and write SNM (WSNM), the back-gating technique is more effective in the subthreshold region than in the superthreshold region. The 6T UTB SOI subthreshold SRAM cell with the back-gating technique by increasing the strength of the pull-up transistors and decreasing the strength of the pass-gate transistors shows comparable RSNM with the 10T bulk subthreshold SRAM and an improvement in RSNM variation. Due to better electrostatic integrity, the back-gating technique (pull-up transistors with positive back-gate bias, pull-down/pass-gate transistors with negative back-gate bias) mitigates the 6T UTB SOI SRAM RSNM variation significantly with some improvement in RSNM. Increasing cell beta-ratio shows a limited improvement on RSNM and has no benefit on the SNM variability for the subthreshold operation. The UTB SOI 8T SRAM cell exhibits RSNM 2times larger than the 6T SRAM cell in the subthreshold region. Both negative bit-line voltage (VBL) and boosted word-line voltage (VWL) are more effective than lower cell supply voltage to improve WSNM, and negative VBL shows a larger improvement in WSNM than boosted VWL.

The conventional SRAMs, namely four-transistor SRAM (4T) and six-transistor SRAM (6T), suffered from the external noise, because they have direct paths through bit-line(BL) to their storage nodes. This paper proposes seven-transistor (7T) SRAM which has no direct path through BL to the data storage nodes and has higher endurance against external noise. The proposed cell is composed of two separate data access mechanisms; one is for the read operation and another is for the write one. Based upon our SRAM design, data destruction never occurs in the read operation. Simulation result shows that the read Static-Noise-Margin (SNM) of the proposed cell is enhanced by 1.6X and 0.31X with the conventional 4T and 6T SRAM cell respectively. We also manufactured a chip and confirmed its performance.

Radiation-induced single-event upsets (SEUs), or soft errors, cause a significant threat to the reliability of nanoscale memories. In this paper, we have proposed a 10-T radiation-hardened SRAM cell with exceptionally high radiation tolerance. The proposed cell has significantly better performance in terms of radiation robustness as compared to other existing radiation-hardened SRAM cells. Comparisons of several hardened memory cells in terms of access time (read access time and write access time), stability (read static noise margin, write margin, and hold static noise margin), power consumption (read power, write power, and hold power), and layout area is done. From these comparisons, it can be concluded that the proposed cell has better or comparable performance for all the parameters, except for write access time (TWA). The write access time is longer for the proposed cell as compared to other comparison cells. Furthermore, the effect of supply voltage variation has also been studied by calculating and comparing all the parameters at different supply voltages. Monte Carlo simulations are also used for some of the parameters to evaluate the effects of process, voltage, and temperature (PVT) variations.

At present day SRAM cell is under renewal stage. Researchers are aiming to get an SRAM cell which is reliable and robust against process, voltage and temperature (PVT) fluctuations. An SRAM cell is also expected to support low-power applications. This article proposes a new way for designing an SRAM cell. The proposed cell functions properly even bellow subthreshold region. Therefore, it can be useful for ultralow-power applications. Robustness/reliability of the proposed design is investigated by estimating read static noise margin (RSNM). The estimated results are compared with its conventional counterpart. The proposed 6T SRAM cell offers 1.83× faster read operation. It is also less affected by PVT fluctuations (by 1.47×) during read operation compared to conventional 6T SRAM cell. The proposed SRAM cell exhibits 1.40× higher RSNM compared to conventional 6T SRAM cell, proving its reliability during read operation. It also shows 3.86% faster write operation. It is 18.4% less affected by PVT fluctuations. It has 2.33% higher write static noise margin (WSNM) than the conventional 6T SRAM cell.

Summary form only given. We consider the soft error sensitivity trends to various memory and logic components as they are scaled to smaller dimensions, higher integration densities, and lower operating voltages. We also review the three radiation mechanisms responsible for soft errors in the terrestrial environment and discuss the methods for characterizing radiation sensitivity and methods for extrapolating product soft error rate (SER) from accelerated tests - with a focus on the difficulties in using test chip SER data to derive actual product mean-time-to-failure from soft errors. We then focus on technology scaling trends for SER, showing that although DRAM bit SER has been reduced by about four to five times per generation, DRAM system failure rates remain unchanged because the amount of system memory has increased as fast as the reductions in DRAM bit SER. We also show that in deep sub-micron regime, the SRAM single bit SER saturates as a function of technology scaling. We also review techniques for reducing SER and conclude that error correction is the beast means of mitigating memory soft errors, and that in high reliability systems that employ error correction on all embedded memory, the product failure rate is limited by the sequential logic SER.

For applications with stringent power budget, such as ultra low power systems and Internet of the things (IoT), power and energy are the most important constraints. It is shown that when the supply voltage is close to the threshold voltage of transistor, known as near threshold computing (NTC), the energy consumption is at its minimum range. However, by reducing the supply voltage not only the circuit performance decreases significantly, but aggravates various reliability mechanisms. Moreover, the performance variation due to process and runtime variation increases exponentially which makes the traditional margining, to address variability, very inefficient. In this paper, we address energy-efficient countermeasures to combat reliability challenges at NTC in order to guarantee resilient and energy-efficient system operation. We propose to partition a functional unit such as Arithmetic Logic Unit (ALU) into multiple smaller and faster functional units and power-gate them whenever they are not used for long time. Simulation results show that by applying the proposed method the energy efficiency of an ALU can be improved by up to 43.4% at NTC with multiple fold reliability improvements due to timing failures.