A computational algorithm for pole assignment of linear multi-input systems

Some points of the paper by N.K. Nichols (see ibid., vol.AC-31, p.643-5, 1986), concerning the robust pole assignment of linear multiinput systems, are clarified. It is stressed that the minimization of the condition number of the closed-loop eigenvector matrix does not necessarily lead to robustness of the pole assignment. It is shown why the computational method, which Nichols claims is robust, is in fact numerically unstable with respect to the determination of the gain matrix. In replying, Nichols presents arguments to support the choice of the conditioning of the closed-loop poles as a measure of robustness and to show that the methods of J Kautsky, N. K. Nichols and P. VanDooren (1985) are stable in the sense that they produce accurate solutions to well-conditioned problems.

A short and direct new proof is given to Wonham's theorem that a time invariant multi-input linear dynamical system is controllable only if its poles can arbitrarily be reassigned in a closed-loop system by means of a constant (state variable) feedback law. The construction provided in the proof is directly applicable as an effective algorithm for this pole assignment.

A new pole-placement algorithm for multi-input controllable systems is presented. The algorithm can be used to obtain real-valued feedback gains for arbitrarily specified real and complex, distinct or multiple eigenvalues. The multi-input controllable time-invariant system is converted to a single-input system. Pole assignment is achieved by making use of certain properties of the equation TF - AT = D , where A is the open-loop system matrix and F represents a matrix having the desired closed-loop eigenvalues.

Macroblock pin assignment and routing are important tasks in physical design. Existing algorithms for these problems can be classified into two categories: 1) a two-step approach where pin assignment is followed by routing and 2) a net-by-net approach where pin assignment and routing for a single net are performed simultaneously. However, none of the existing algorithms is "exact" in the sense that they may fail to route all of the nets even though a feasible solution exists. This remains to be true even if only two-pin nets with fixed pins between two blocks are concerned. In this paper, we consider the problem of two-pin net connections from one macroblock to all of the other blocks, and present the first polynomial-time exact algorithm for simultaneous pin assignment and routing for all of the two-pin nets between one block (source block) and all of the other blocks. In addition to finding a feasible solution whenever one exists, it guarantees to find a pin-assignment/routing solution with minimum cost /spl alpha//spl middot/W+/spl beta//spl middot/V, where W is the total wire length and V is the total number of vias. Our algorithm has various applications. 1) It is suitable in engineering change order (ECO) situations where the existing solution is modified incrementally. 2) Given any pin assignment and routing solution obtained by any existing method, our algorithm can be used to increase the number of routed nets and reduce the routing cost. Furthermore, it provides an efficient algorithm for the pin assignment and routing problem of all of the blocks. The method is applicable to both global and detailed routing with arbitrary routing obstacles on multiple layers. Experimental results demonstrate its efficiency and effectiveness.

Macro-block pin assignment and routing are important tasks in physical design planning. Existing algorithms for these problems can be classified into two categories: 1) a two-step approach where pin assignment is followed by routing, and 2) a net-by-net approach where pin assignment and routing for a single net are performed simultaneously. None of the existing algorithms is in the sense that the algorithm may fail to route all nets even though a feasible solution exists. This remains to be true even if only 2-pin nets between two blocks are concerned. In this paper, we present the first polynomial-time exact algorithm for simultaneous pin assignment and routing for 2-pin nets from one block (source block) to all other blocks. In addition to finding a feasible solution whenever one exists, it guarantees to find a pin-assignment/routing solution with minimum cost α · W + β · V, where W is the total wirelength and V is the total number of vias. Our algorithm has various applications: 1) It is suitable in ECO (Engineering Change Order) situations where a designer wants to incrementally modify the existing solution instead of redoing everything after a design change. 2) Given any pin assignment and routing solution obtained by any existing method, our algorithm can be used to increase the number of routed nets and reduce the routing cost. Furthermore, it provides an efficient algorithm for the pin assignment and routing problem of all blocks. The method is applicable to both global and detailed routing with arbitrary routing obstacles on multiple layers. Experimental results demonstrate its efficiency and effectiveness.

Two regularization methods for ill-conditioned least squares problems are studied from the point of view of numerical efficiency. The regularization methods are formulated as quadratically constrained least squares problems, and it is shown that if they are transformed into a certain standard form, very efficient algorithms can be used for their solution. New algorithms are given, both for the transformation and for the regularization methods in standard form. A comparison to previous algorithms is made and it is shown that the overall efficiency (in terms of the number of arithmetic operations) of the new algorithms is better.

Circular permutation of a protein is a genetic operation in which part of the C-terminal of the protein is moved to its N-terminal. Recently, it has been shown that proteins that undergo engineered circular permutations generally maintain their three dimensional structure and biological function. This observation raises the possibility that circular permutation has occurred in Nature during evolution. In this scenario a protein underwent circular permutation into another protein, thereafter both proteins further diverged by standard genetic operations. To study this possibility one needs an efficient algorithm that for a given pair of proteins can detect the underlying event of circular permutations. A possible formal description of the question is: given two sequences, find a circular permutation of one of them under which the edit distance between the proteins is minimal. A naive algorithm might take time proportional to N3 or even N4, which is prohibitively slow for a large-scale survey. A sophisticated algorithm that runs in asymptotic time of N2 was recently suggested, but it is not practical for a large-scale survey. A simple and efficient algorithm that runs in time N2 is presented. The algorithm is based on duplicating one of the two sequences, and then performing a modified version of the standard dynamic programming algorithm. While the algorithm is not guaranteed to find the optimal results, we present data that indicate that in practice the algorithm performs very well. A Fortran program that calculates the optimal edit distance under circular permutation is available upon request from the authors. ron@biocom1.ls.biu.ac.il.

Accelerated generalized successive overrelaxation method for least squares problems

In this paper a new numerical algorithm for pole assignment of linear time-invariant systems is presented. The proposed algorithm uses reliable numerical techniques based on the Schur form of the state matrix and on the use of orthogonal transformations. Only the "bad" eigenvalues of the system are modified by a sequential pole-shifting procedure, and the resulted gains in the feedback matrix are minimized.

The radio frequency spectrum, a scarce resource in mobile communications, has to be efficiently utilized with the objective of increasing the network capacity and minimizing the interference. A variety of channel assignment strategies have been developed to achieve these objectives. Not only the mobility of the wireless user but also different types of wireless multimedia services create uncertainty in demand and non-optimum use of radio resources. As the cell sizes get smaller, there is a greater need for efficient channel assignment algorithms which are desired to dynamically balance the load of the system by performing reassignments when needed. Static schemes are no longer desirable for small cell systems under heavy and non-uniform multi-rate traffic. We propose a dynamic multi-channel assignment algorithm where the assignment decision is assisted by the mobiles. Our algorithm is based on the concept of network flows, which provide us with the framework to uniformly handle all the events occurring in the system including possible degradation and improvement of the existing assignments. This model enables fast local computations and avoids global reconfiguration which prevent other algorithms being practical.

In this paper we present a simple but efficient timing-driven placement algorithm for FPGAs. The algorithm computes forces acting on a logic block in the FPGA to determine its relative location with respect to other blocks. The forces depend on the criticality of nets shared between the two blocks. Unlike other net-based approaches, timing constraints are incorporated directly into the force equations to guide the placement. Slot assignment is then used to move the blocks into valid slot locations on the FPGA chip. The assignment algorithm also makes use of the delay information of nets so that the final placement is able to meet the timing criteria specified for the circuit. The novelty of the approach lies in the formulation of the force equations and the manner in which weights of the nets are dynamically altered to influence the placement. Experiments conducted on industrial test circuits and MCNC circuits give very promising results and indicate that the algorithm succeeds in significantly reducing the maximum delay in the circuit. In addition, routability is not adversely affected and running time is low.

Energy efficient design for hardware and software implementations plays an important role in pivoting the system towards reliability without any considerable limitations. Energy consumption is a critical design issue in real time system. The main challenge in battery operated system is maintaining high performance. Dynamic voltage scaling and dynamic frequency scaling is used to adjust supply voltage and processor frequency to adapt the workload demand for better energy management. From the literature survey, the problem of local optima, resources constraints, task assignment and scheduling are identified for energy management. To solve these problems, local with restarts algorithm (LSR) and voltage assignment algorithms (PVAP) are proposed to address the problem of Processor and Voltage Assignment with Probability by adopting a probabilistic approach of tasks in real-time embedded systems. A task DAG (Directed Acyclic Graph) is used to model the PVAP problem. In order to facilitate dynamic voltage scaling, voltage assignment algorithm is worked out with execution time and energy units as considerations and it encounters a common node problem. As an effective aid local search with restarts algorithm is used this proves effective against local optima too. The experiment has been done on different benchmark sets.

Two efficient heuristic time slot assignment (TSA) algorithms, called the 2-Phase algorithm for the non-hierarchical and the 3-Phase algorithm for the hierarchical TDM switching systems, are proposed. Their time complexities are O(LN/sup 2/) and O(LM/sup 2/) respectively, where L is the frame length, N is the switch size and M is the number of input/output sources connected to a hierarchical TDM switch. The simple idea behind these two algorithms is to schedule the traffic on the critical lines/trunks of a traffic matrix first. Extensive simulations reveal that the two proposed algorithms are very efficient. For non-hierarchical TDM switching systems, P/sub F/ the probability that the 2-Phase algorithm failed to generate optimal TSAs is found to be 3/spl times/10/sup -5/ and independent of switch size. For hierarchical switching systems, the percentage increase in frame length as a result of non-optimal TSA by the 3-Phase algorithm is about 0.1%. That means on the average only one extra time slot is required for a frame of 1000 time slots.

The problem of pole assignment in linear, multivariable systems using an unconstrained-rank feedback matrix is considered. The effect of output feedback of unspecified rank on the characteristic polynomial of a multivariable system is first studied. The results are then used to derive a recursive algorithm for pole assignment without any restrictions on the rank of the output feedback matrix used. The method is based on the pseudoinverse concept for obtaining least-squares solutions of sets of linear equations, and is computationally efficient.

Linear dynamical systems over finite rings