A constraint driven approach to loop pipelining and register binding

Predicated execution is an efficient mechanism to avoid conditional constructs in application programs. In this paper we describe how an existing method for register binding can be extended to support predicated execution. The method exploits the combination of register constraints, resource and timing constraints and models the overlap of value lifetimes in a conflict graph. In our extension, mutually exclusive values are identified and are used for reconstructing the conflict graph. Register binding for predicated execution in case of software pipelining is also addressed in this paper. Experiments in the Facts environment show that the register pressure is greatly reduced with this technique.

Time constraints related issues are unavoidable tasks in wafer fabrications, especially for back-end copper-interconnect process while the wafers are processed through sets of continuous operations associate with various time constraints. We shall address ourselves to capacity planning in order to eradicate the difficulties of sequential time constraints. This paper proposed a tool portfolio determination model to determine the required quantity and type of tools for ensuring pre-defined target yield could be achieved. The workstations are modeled as GI/G/m queuing network, and the analysis of rate of wafers exceeding queue time is adopted to determine the required capacity. Furthermore, a virtual customer was introduced into the model to adjust system service rate to character the machine failure. By this approach, the influence of downtime duration at fixed machine availability could be observed. The results support that the proposed model can more effectively resolve the issues of sequential time constraints. Moreover, the analysis results indicate that the current capacity expansion policy of the semiconductor industry should be re-examined.

A window-assisted video partitioning strategy for partitioning and caching video streams in distributed multimedia systems

In this work, we address the multiple voltage scheduling problem to minimize power consumption under both timing and resource constraints. We develop a tabu search-based algorithm with a general vector representation of solution and an effective performance estimation. Moreover, our approach tends to solve a series of scheduling problems with respect to multiple voltage designs. Specifically, our method represents each solution by a vector of operation types and solves the scheduling subproblem corresponding to a certain solution vector. To get feasible solutions of the subproblem, a two-stage method is presented by first adopting the PLNSM algorithm [3] to generate delay assignment satisfying the timing constraint and then performing delay adjustment iteratively until the resource constraints are met. A heuristic estimation is introduced to predict the total power and resource usage of the neighborhood. Our proposed method achieves near-optimal solutions with only an average power increase of 0.84% compared with ILP for small-size designs, and a 24.1% reduction over a previous tabu search-based algorithm [7] for a set of benchmarks.

In this paper, a scheduling algorithm for multi-processor real-time systems with relative timing constraints and resource constraints is proposed. The proposed algorithm has the capability to satisfy any timing constraints expressed as inequalities in two variables and a constant. This implies that scheduling problems imposed on various timing constraints such as end-to-end timing constraints and/or relative timing constraints, which are known to be difficult to handle, can be solved. Since the problem addressed in this paper is a generalization of some NP-complete problems, it is difficult to solve efficiently. Thus, the goal of the authors is to derive a heuristic algorithm which performs well on many instances of the problem, although in some cases it will take enormous space and time. Experimental results show that the proposed algorithm achieves a success rate of 80% in 3 minutes of computation time.

Effective and efficient modelling and management of hardware resources have always been critical toward generating highly efficient code in optimizing compilers. The instruction templates and dispersal rules of the EPIC architecture add new complexity in managing resource constraints to instruction scheduler. We extended a finite state automaton (FSA) approach to efficiently manage all key resource constraints of an EPIC architecture on-the-fly during instruction scheduling. We have fully integrated the FSA-based resource management into the instruction scheduler in the Open Research Compiler for the EPIC architecture. Our integrated approach shows up to 12% speedup on some SPECint2000 benchmarks and 4.5% speedup on average for all SPECint2000 benchmarks on an Itanium machine when compares to an instruction scheduler with decoupled resource management. In the meantime, the instruction scheduling time of our approach is reduced by 4% on average.

Lean strategies have been developed to eliminate or reduce waste and thus improve operational efficiency in a manufacturing environment. However, in practice, manufacturers encounter difficulties to select appropriate lean strategies within their resource constraints and to quantitatively evaluate the perceived value of manufacturing waste reduction. This paper presents a methodology developed to quantitatively evaluate the contribution of lean strategies selected to reduce manufacturing wastes within the manufacturers’ resource (time) constraints. A mathematical model has been developed for evaluating the perceived value of lean strategies to manufacturing waste reduction and a step-by-step methodology is provided for selecting appropriate lean strategies to improve the manufacturing performance within their resource constraints. A computer program is developed in MATLAB for finding the optimum solution. With the help of a case study, the proposed methodology and developed model has been validated. A ‘lean strategy-wastes’ correlation matrix has been proposed to establish the relationship between the manufacturing wastes and lean strategies. Using the correlation matrix and applying the proposed methodology and developed mathematical model, authors came out with optimised perceived value of reduction of a manufacturer's wastes by implementing appropriate lean strategies within a manufacturer's resources constraints. Results also demonstrate that the perceived value of reduction of manufacturing wastes can significantly be changed based on policies and product strategy taken by a manufacturer. The proposed methodology can also be used in dynamic situations by changing the input in the programme developed in MATLAB. By identifying appropriate lean strategies for specific manufacturing wastes, a manufacturer can better prioritise implementation efforts and resources to maximise the success of implementing lean strategies in their organisation.

Nowadays, there appeared a tendency of expanding scope and scale of activities in the Arctic. This is accompanied by the increasing number of security threats and potential emergencies factors in the region. Arctic region development involves implementing the goals of reducing risks to global and regional security. An important role in implementing the strategy of creating a comprehensive security system in the Arctic belongs to efficient protection of population and territories, critically important and potentially dangerous facilities from natural and man-made emergencies. All dangerous factors characterizing emergencies require generation of a complex approach to ensure security in the Arctic territories, increasing the rescue services resource potential and providing monitoring the environment components state and pollution. This article identifies ways to solve the problem of strategic planning and deployment of forces and facilities when creating an integrated security system under resource constraints and dynamically changing situation in the Arctic. An organization chart of strategic resource planning for emergencies management in the Arctic was developed. A decision-making algorithm is proposed to elaborate forces and facilitate composition for the Arctic integrated search-and-rescue centers based on the developed chart. Achieving results in strategic planning involves elaboration of a program for developing forces and facilities of the integrated security system in the Arctic region on the basis of results obtained within the simulation process. The program should reflect step-by-step solution of strategic planning tasks in accordance with goals, resource and time constraints.

In the past, a variety of approximate functional units have been developed, out of which some approximate functional units can dynamically change the degree of computation accuracy. The more inaccurately they compute, the faster they do. This paper studies high-level synthesis of approximate circuits which efficiently utilizes such accuracy-controllable functional units with variable latency. Under resource and time constraints, our scheduling method tries to minimize the computation error of the output by selectively multicycling operations. In the experiments, we explore the trade-off between performance, hardware cost and accuracy to demonstrate the effectiveness of this work.

Hardware/software partitioning aiming at fulfilment of real-time constraints

The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler phases include instruction scheduling, which maximizes instruction level parallelism (ILP), and register allocation, which minimizes data spills to external memory. If ILP is maximized without considering register constraints, high register pressure may result, leading to increased spill code and reduced run-time performance. In this paper, a new register pressure reduction technique for embedded VLIW processors is presented to control register pressure prior to instruction scheduling and register allocation. By modifying the relative ordering of operations, this technique restructures code to better reduce spills. Our technique has been implemented in Trimaran, an academic VLIW compiler, and evaluated using a series of VLIW benchmarks. Experimental results show that, on average, our algorithm reduces dynamic spills and improves overall cycle counts by 6% for a VLIW architecture with 8 functional units and 32 registers versus previous spill code reduction techniques.

This study explored the use of blended learning in a fashion design class, working within the constructivist orientation with a mixed methods case study and using a sequential exploratory approach in order to focus on the effectiveness of the blended learning design and how it is experienced by the participants. The case study was based on a group of second year fashion design students from a private design institution in South Africa, for the combined subject, pattern making and garment construction. The purpose of this research was to investigate the ways in which face-to-face learning and online learning could best be blended to facilitate instruction in this particular class. The study focused on establishing what combination of online and face-to-face delivery could be seen to be most effective in achieving the project learning outcomes within the time and resource constraints available for the combined pattern making and garment construction subject. A blended learning curriculum model (Huang, Ma and Zhang, 2008) was used to assist in preparation for the blended learning programme, with online learning delivery being effected by means of Google Classroom, the learning management system recommended by the private design institution. The sequential exploratory approach involved two projects, so that insights gained from the first project could be applied to modify the blended learning design for the second project, if and as required. Quantitative data were used to establish a baseline of students’ prior understanding of blended learning, pattern making and garment construction processes. Qualitative data were collected in the form of interviews, questionnaires and observations, allowing for a descriptive understanding of how students as well as the lecturer (who was the researcher) experienced the blended learning classroom, and how effective that blend was in achieving the desired learning outcomes; opportunities were also offered for reflection. The results revealed that, not only did blended learning delivery need to be applied in a developmental way, with ongoing adjustments to accommodate best teaching/learning practice, but also that different fashion ‘briefs’ (that is, the tasks involved) might require modifications to the blended learning delivery design. This suggests that there is no ideal ‘blend’ in blended learning, but that, like other forms of learning, it is exploratory, tentative and constantly evolving. It is hoped that this study will offer insights into how face-to-face and online learning can be combined to best facilitate the learning process in this particular case, where practical assistance with students’ individual design projects traditionally requires a large amount of the instructional time available. As many vocational university subjects have similar time and resource constraints, particularly in facilitating practical application of theory at a professional standard, it is also hoped that, to some extent, the results will be generalizable to other disciplines.

This study aimed to explore what happened in the experiences of eight Grade 3-5 teachers when they provided small group strategies to students with learning disabilities at United Cerebral Palsy of Central Florida, Pine Hills. The research employed semi-structured interviews to investigate difficulties and perceptions. Teachers discussed positive effects on students' performance, engagement, and confidence. But there were many hurdles too, like managing a wide range of behaviors and skill levels, toggling between small-group and whole-group instruction, and meeting the emotional needs of each student. Resource constraints (material, technology, support personnel) only compounded these challenges. Thematic analysis highlighted the following themes: Classroom management, time constraints, different learning requirements, resource constraints, and social-emotional challenges. This study adds to the fund of knowledge by identifying the challenges and successes of small group strategies for LD. The importance of improving teacher preparation about inclusive practice, differentiation, and behaviour management, as well as providing more resources and support staff, is highlighted. Small group instruction significantly improves academic performance among students with learning disabilities by allowing for personalized instruction and increased engagement. However, its success depends on adequate support, including time, staffing, and behavioral strategies, to ensure effective and sustainable implementation. Continuous professional development and strong institutional backing are crucial to empower teachers in delivering dynamic, differentiated instruction tailored to diverse learner needs. Based on the conclusions, it is recommended that schools formally adopt small-group instruction as a core strategy in inclusive education and provide dedicated time and support staff for its implementation. Training in differentiated instruction, behavior management, and collaborative planning should be regularly conducted to equip teachers with inclusive practices. Adequate learning resources, assistive tools, and data-informed grouping strategies are essential to address diverse student needs. Lastly, applying the Enhanced Support Program for Students with Learning Disabilities (ESP-SLD) and fostering teamwork among educators, parents, and peers will strengthen inclusive efforts and improve student outcomes.

Present-day digital systems are characterized by large complexity, operation under tight timing constraints, numerous false paths, and large variations in component delays. In such a scenario, it is very important to ensure correct temporal behavior of these circuits, both before and after fabrication. For combinational circuits, it has been shown that it is necessary and sufficient to guarantee that the primitive path delay faults (PDFs) are fault-free to ensure that the circuit operates correctly for some timing constraint T and all larger timing constraints. We show that primitive PDFs determine the stabilization time of the circuit outputs, based on which we develop a feasible method to identify the primitive PDFs in a general multilevel logic circuit. We prove that the maximum primitive PDF delay is exactly equal to the maximum circuit delay found under the floating mode of operation assumption. From this result, we devise a method to perform timing analysis based on primitive PDF identification which delinks functional analysis from delay computation. Our timing analysis approach provides several advantages over previously reported floating mode timing analyzers: increased accuracy in the presence of component delay correlations and signal correlations arising from fabrication process, signal propagation, and signal interaction effects; increased efficiency in situations where critical paths need to be re-identified due to component delay speedup (e.g., post-layout delay optimization). We demonstrate the applicability of our timing analysis approach for a variety of benchmark circuits, and demonstrate the pessimism of conventional floating mode timing analysis approaches in accounting for signal propagation effects.

This paper describes the features of the HARTIK system, a hard real-time kernel designed to help the development of real-time applications, ranging from classical hard control systems to soft multimedia, distributed systems. The portability, the predictability and the flexibility in expressing timing constraints allow the application designer to explore a broad set of solutions both from a hardware and software perspective. A toolkit has also been developed to support the design phase. The kernel supports 16-bit and 32-bit Intel 80/spl times/86 processors, DEC Alpha AXP-PCI-33, and can be easily ported to other different hardware architectures, such as microcontrollers and embedded systems. The relevant features offered by the kernel include direct specification of timing constraints, such us period and deadlines, coexistence of tasks with different criticalness, dynamic scheduling of periodic and aperiodic tasks, bounded blocking time on shared resources, prevention of deadlock and chained blocking; asynchronous, time bounded communication paradigm for exchanging data among tasks having different execution rates.