A Counter-based SR Forward Converter with Standby Power Reduction Considered

In this paper, the field programmable gate arrays (FPGA) technique is used to control the flyback converter. The proposed control loop design, together with the one-comparator counter-based PWM control strategy without any analog-to digital converter (ADC) used is presented and applied to controlling the flyback converter under the discontinuous current mode (DCM). The detailed illustration of the proposed control scheme is provided, together with some experimental results to verify its effectiveness.

This paper proposes a discontinuous current mode (DCM) feedback current control for a single-phase grid-tied inverter in order to minimize a LCL filter without worsening total harmonic distortion (THD) of a grid current. In DCM, there are two nonlinearities occurring in the transfer functions; the first non-linearity occurs in the duty-ratio-to-current transfer function which worsens the current command response, whereas the second nonlinearity occurs in the disturbance-to-current transfer function which reduces the disturbance effect. In the proposed DCM current control, the first nonlinearity is compensated by utilizing the duty ratio at the previous calculation period in order to achieve the same control performance of the current command response as in continuous current mode. Meanwhile, the second nonlinearity is utilized in order to reduce the disturbance effect when the LCL filter with a small impedance is applied. Furthermore, a design procedure of the LCL filter is introduced under the condition that the impedance of the LCL filter can be minimized without worsening the grid current THD by applying the proposed DCM control. A 1-kW 100-kHz inverter with several LCL filters of different impedances (3.0%, 0.6% and 0.04%) is constructed in order to confirm the operation of the proposed DCM current control. As a result, the grid current THD is reduced from 8.5% to 3.7% at rated load. Furthermore, the inductor volume is reduced by 77.0%, whereas the converter loss is reduced by 17.1%.

Three-phase synchronous generator-rectifier systems (TPSGRSs) with LC filters would exist discontinuous current mode (DCM) at their DC sides in cases of light loading or large filter capacitors contained. It is difficult to establish mathematical model of these generator-rectifier systems operating in DCM. To solve this problem, a new modeling method is proposed by substituting controlled rectifier in series with Boost circuit for diode rectifier in a TPSGRS. Considering the influence of inner resistances of inductances, we establish a new large signal mathematical model of TPSGRSs using switching function and principle of harmonic balance. The new model is compared to detailed simulations as well as physical tests, and is validated to be accurate in capturing large disturbance behaviors of TPSGRS operating in both continuous current mode (CCM) and DCM.

The state-space modeling and related order reduction problems of switching DC-DC converters operating in discontinuous (D) mode are treated in this paper. A unified discrete-time full-order model is proposed assuming the discontinuous current and voltage mode (DCVM) as a general operation mode from which the discontinuous current mode (DCM), the discontinuous voltage mode (DVM), and continuous made (CM) derive as special cases. Such a model permits a straightforward study of the control-to-output response, in each operation mode. The order reduction of the transfer function is carried out by means of the principal component analysis considering the joint controllability and observability properties of the circuit. It is shown that a proper order reduction can be gained not only in DC mode, as expected, but also in DV and DCV modes. A substantial difference between DC and DV modes is also evidenced in terms of controllability. The frequency analysis and state-space model order reduction for a Cuk converter are proposed to show that the method is free of the limitations affecting other methods of analysis and that its predictions fit experimental measurements.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A design methodology is presented for a full-bridge Power Factor Corrector (PFC) converter with two control schemes: the well-known Continuous Current Mode (C.C.M) and Triangular Current Mode (T.C.M). The second one is an extension of the Discontinuous Current Mode (D.C.M). The converter is composed of one high frequency leg and one leg switching at the grid frequency and includes the EMC (common and differential mode) filter. This work highlights the impact of the modulation scheme on the design of passive components and on the overall losses. A pareto front in the efficiency (η) vs power density (ρ) domain is derived for both modulation schemes and for natural convection cooling. We show that, when EMC issues are considered, the T.C.M poses more constraints for partial load operation, superseding the full-load design. Finally, it is shown that for non-interleaved converters C.C.M modulation is better than T.C.M modulation, resulting in higher density converters.

This paper deals with the evaluation of a comparative design of power inductors in two legs interleaved boost Power Factor Corrector (PFC) converter applied as front-end in 3.3kW battery charger for electric vehicles. The boost inductors have been designed and compared in the PFC application in Continuous Current Mode (CCM) and Discontinuous Current Mode (DCM) operation. A procedure to design the inductors in its electrical and magnetic parts procedure based on MATLAB scripts is described. The interleaved boost inductor power losses are evaluated. The leg current switching behavior in an actual PFC converter with the inductors carried out from the design procedure is presented. Finally, the advantages and drawbacks of the inductor in CCM and DCM operating conditions are discussed.

The paper presents a proposed design of SEPIC with high voltage gain for sustainable energy applications. The suggested circuit is structured by combining the standard SEPIC with a magnifying module. Hence the converter profits from various assets that the specific converter has, like uninterrupted input current. Also, high voltage gain and input current continuity makes the proposed converter applicable for sustainable energy sources. The altered SEPIC converter (MSC) gives higher voltage gain compared to standard SEPIC and recently addressed converters with single-controlled switch. The analysis of voltage gain in continuous current mode (CCM) and discontinuous current mode (DCM) is carried out by considering the non-idealities of semiconductor devices and passive components. The preference of semiconductor devices depending on voltage- current rating is put forward along with the designing of reactive components. The numerical simulation and experimental work is done and the results demonstrate viability of the MSC concept and theoretical analysis.

This article suggests a unified modeling approach to the analysis of tapped-inductor converters. The leakage inductance, inherent to coupled magnetic structures, and the associated snubber circuit effects were considered and incorporated into the suggested model. The proposed nonideal tapped inductor switcher model is formulated as an equivalent subgraph that can help to model most, if not all, converter topologies that comprise a two-winding tapped inductor. Both the continuous current mode and the discontinuous current mode were modeled. To validate the proposed approach, analysis of a Flyback converter with an <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> snubber is presented. Theoretical prediction of the steady-state and small-signal behavior of the converters were confirmed by simulation and experimental results.

The comparison of the power stage dynamics between a conventional LLC converter and a three-level LLC converter is presented in this paper. The frequency response was similar in continuous current mode, but different in discontinuous current mode. Moreover, how the variation of circuit parameters affects the transfer function of the three-level LLC converter is studied. The experimental verification is provided as well.

A Mixed Logic Dynamic (MLD) model and control method based on mode selection are proposed for the Buck convertor. In establishing the hybrid system model, the factors such as the inductor current are neglected, and the Model Predictive Control (MPC) is used to switch the most favorable working state of the control target. Since the modeling process ignores the inductance and current, it is necessary to convert the optimization prediction control resulting to avoid the problem that the model is inconsistent with the control object. The method proposed in this paper uses fewer auxiliary logic variables and mixed logic variables in the modeling process, simplifying the model and improving the solution speed. This method can not only make the Buck converter work in the Continuous Current Mode (CCM) but also work in the Discontinuous Current Mode (DCM), extending the adjustment range of the Buck converter. The simulation results show that the proposed method has a better control performance than the traditional MLD model.

A detailed analysis of DC-DC buck and boost converters operated both in continuous and discontinuous current modes is reported. Expressions for the voltage transfer functions and efficiencies of these two basic topologies have been derived in a closed form. These equations describe the converter behaviour for both constant output voltage and constant input voltage operation. Voltage transfer functions are derived so that the load regulation characteristics of the converters are closely described, including those for continuous current mode operation. Because of this, they can be effectively used to design a converter circuit responding to any given design specification. Both the equations for the efficiencies and voltage transfer functions are general and the values of the parasitic parameters to be introduced can be found on the component data sheets or derived from simple measurements. Because of this, results of the analysis presented can be effectively used in the optimization of the converter circuit...

Approximate expressions for the calculation of the load and control characteristics of the direct-voltage transducer were obtained by the fundamental harmonics method on the basis of the linear equivalent circuit of a direct-voltage transducer constructed on the assumption of current harmonicity in the series LC circuit. Comparison of the load characteristics constructed according to the grounded exact method based on the fitting method and the obtained approximate formulas shows that the fundamental harmonic method may be used for calculation of the static characteristics at the phase regulation in the continuous current mode with acceptable practical accuracy. In the discontinuous current mode, the method gives an overestimated output voltage, with the exception of the mode close to idling, where the voltage values are underestimated. The error of the basic harmonic method increases with the decrease in the relative duration of the pulses at the output of the inverter bridge.

The conventional rectifier [1] which is popularly referred as Unity Power Rectifiers (UPR)/ Boost rectifier (BR) suffers from various limitations such as low power factor, high ripple content on load voltage and increase in harmonic contents in source current due to non-linear load current that results in significant increase of total harmonic distortion (THD). The main objective of conventional SMR (i.e. shown in Fig.1) is to eliminate these problems so as to maintain unity pf, sinusoidal input current, constant dc voltage and restricted harmonic distortion based on IEEE std. To avoid the separate operation for discontinuous current mode (DCM) and continuous current mode (CCM), a mixed-mode operation [2] is proposed for wide-range of load variation. Since the ripple content on output capacitor voltage and harmonic contents in input ac current are prime concern, the authors [3] presented a robust technique to get rid of these problems. In SMR, the power flow is unidirectional and the circuit is to be operated as boost switch which enables the capacitor to keep the voltage slightly greater than peak of source voltage. But in order to double the level of capacitor voltage with respect to input voltage, a new topology [4] is proposed by Y.Neba and et.al. All these SMRs operate for resistive load, but Patil and et.al[5] changed this resistive load to induction motor to study its effect upon SMR. The mixed-mode operation [2], which has some limitations, has been overcome by modifying the SMR [6]. The topologies used [1-8] use boost inductor on dc side. So this suffers from following demerits.

This paper proposes a development of Pulse-Width Modulation (PWM) switching signals based on Field Programmable Logic Array (FPGA) and Digital Signal Processor (DSP) to control multi-input interleaved DC/DC converter (MIC). The proposed PWM signals for the MIC do not only require a control of duty cycle, but also operation at different PWM frequency. In order to solve this problem, a simple programmable control scheme using a digital controller can be employed to facilitate the realization of PWM signals generation. The PWM signals are designed by using Altera Cyclone II FPGA board. The duty cycle employed to regulate output voltage is attained from the dSPACE DS1103 board using a Proportional-Integral (PI) controller. This paper also highlights design guidelines, simulation and experimental results. Experiment results show that the proposed DC converter can be driven by PWM signals, by integration of both controllers.

Drain-source synchronous rectification (SR) is a technique used to reduce the secondary-side conduction loss of an LLC resonant converter. In drain-source sensed SR, an early turn off issue can be observed due to parasitics in the drain-source voltage sensing loop. In LLC converter rectifiers where multiple SR switches are paralleled, sequential parallel switching (SPS) can be implemented to sequentially turn off the SR FETs to reduce the effect of these parasitics. By turning off SR FETs one by one over batch turn-off, the drain-source voltage signal near the turn-off moment can be enhanced, mitigating the effects of parasitics and the subsequent early turn-off issue. This method also reduces the amount of turn-off jitter experienced with low on-resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS,on</sub> ) FETs, which can start a detrimental resonance at light load conditions. Since the SR conduction time is prolonged, SPS can decrease body-diode/anti-parallel-diode conduction loss in the rectifier. This results in a net increase in converter efficiency, despite a slight increase in the SR FET's channel conduction loss. The concept and operation of SPS is proposed, explained, and simulated in this paper. Finally, SPS is implemented and verified at light load on a LLC resonant converter with paralleled GaN SR FETs.