A Cyclic Vernier TDC for ADPLLs Synthesized From a Standard Cell Library

An all-digital phase-locked loop (ADPLL) with all components working with time interval or period signals is demonstrated. The ADPLL consists mainly of a free-running ring oscillator (FRO), a time to digital converter (TDC), a digitally controlled oscillator (DCO), a digital divider and a digital loop filter. In the proposed architecture, the TDC and DCO have an equal time resolution from the common FRO. The digital divider keeps the loop gain constant when the frequency multiplication factor changes. As a result, the ADPLL is inherently stable regardless of the variations of the process, supply voltage and temperature (PVT). The ADPLL is fabricated in 0.13 ¿m CMOS process. Measurement results show that it works well over wide operation conditions, with the input frequencies ranging from 37.5 KHz to 25 MHz, frequency multiplication factors from 10 to 255, output frequencies from 10 MHz to 500 MHz, and supply voltages from 0.6 V to 1.6 V.

In this paper, we propose a low-power all-digital phase- locked loop (ADPLL) with a wide input range and a high resolution time-to-digital converter (TDC). The resolution of the proposed TDC is improved by using a phase-interpolator and the time amplifier. The phase noise of the proposed ADPLL is improved by using a fine resolution digitally controlled oscillator (DCO) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. The die area of the ADPLL is 0.8 mm2 using 0.13 µm CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is -120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.

This paper presents a low power, low jitter, PVT-stable film-bulk acoustic wave resonator (FBAR) based all digital phase-locked loop (ADPLL) in a 65nm CMOS process. We introduce a power-efficient integer-N ADPLL architecture, where the digitally-controlled FBAR oscillator (FBAR DCO) achieves phase-lock to a reference clock without any explicit frequency dividers in the feedback path. The simplified divider-less ADPLL has a reduced phase difference at the input of the phase-frequency detector, avoiding a lengthy power hungry time-to-digital converter (TDC). The ADPLL consumes 1.5mW of power and has a measured integrated RMS jitter 0.19ps from 10kHz to 40MHz frequency offset at 1.5GHz carrier frequency. The measured frequency tuning range of 6300ppm for this ADPLL is wide enough to cover the FBAR frequency variations over PVT and provide moderate frequency modulation or channelization. This low power high performance FBAR ADPLL can be used in low power radios, high performance ADCs, and high speed data links.

This paper presents a new quantization noise suppression method for a time-to-digital converter (TDC) and proposes an all-digital phase-locked loop (ADPLL) architecture using only standard cell logic gates. Using a new multiple input multiple output (MIMO) quantization noise suppression method provides an order of $\sqrt {2N} $ improvement in TDC resolution with $N$ parallel TDC channels. Suppressed noise in the TDC allows the ADPLL to achieve superior jitter performance in both theoretical calculations and simulation results. In order to allow fast portability between process nodes, short design cycle time, ease of modification, and flexibility, ADPLL architecture is designed completely in register transfer level intensive Verilog code and the implementation is synthesized in order to obtain final microelectronic design schematics. In comparison to similar work in the literature, postlayout simulation results show that the designed ADPLL achieves period jitter of 1.78 ps$_{rms}$ with a layout area of 0.09 mm$^{2}$ in 65 nm CMOS process and power consumption of 17.5 mW at 800 MHz.

WiMAX (Worldwide Inter-operability for Microwave Access) is an emerging wireless technology standard, which enables high-speed packet data access. To anticipate future demands of WiMAX technology, we propose an all-digital phase-locked loop (ADPLL) based frequency synthesizer for the WiMAX RF transceiver. The developed ADPLL targets frequencies from 2.3–2.7 GHz and from 3.3–3.8 GHz for low band and high band, respectively. A key component of the ADPLL is a time-to-digital converter (TDC), which replaces the traditional phase/frequency detector and charge-pump. The TDC implementation in 40-nm CMOS technology is chosen and presented in this paper. The TDC architecture is based on a pseudo-differential structure. The TDC system has been verified at 1.2 V of power supply, 33.868 MHz frequency reference (FREF) clock and 4.25 GHz output RF frequency. It is found that the power consumption is about 2.99 mW without a clock gating scheme, but is expected to be reduced to 0.78 mW with the clock gating scheme. The INL and DNL of the TDC is lower than 0.4 LSB. The TDC resolution is between 10.84–12.55 ps. At the worst case condition, the TDC resolution of 12.55 ps will produce the in-band phase noise better than −95 dBc/Hz as required by WiMAX ADPLL system. The TDC core layout has a silicon area of only 125×11 µm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

An all-digital phase locked loop (ADPLL) with a proposed time-to-digital converter (TDC) which has no delay cell is designed by the 0.13- μm CMOS process. The delay-cell-less TDC (DLTDC) that can suppress device noises and PVT mismatches is essential for wider bandwidth operations. Moreover, sub-gate TDC resolution can be achieved with the proposed DLTDC. A ring-VCO based digitally-controlled oscillator (DCO) which reduces 1/f noise is also proposed to enhance noise performance. The 2 MHz BW ADPLL which occupies 0.42 mm2 consumes 12 mA and its measured jitter is 4 psrms at 2.4 GHz.

We present an all-digital phase-locked loop (ADPLL)-based frequency synthesizer for WiMAX applications implemented in 40-nm CMOS. Via frequency planning and design of multiple capacitor-banks in a digitally-controlled oscillator (DCO), the ADPLL covers dual bands of 2.3-2.7 GHz and 3.3-3.8 GHz, while achieving a fine frequency resolution of 25 Hz. The time-to-digital converter (TDC) achieves a resolution of better than 13 ps. Several techniques have been proposed to improve system performance. The whole system is simulated via Verilog-AMS with digital circuits at the gate level. The ADPLL achieves an integrated phase noise of better than -40 dBc from 1 kHz to 10 MHz, and settling time is within 15 us.

An all-digital phase-locked loop (ADPLL) for high-speed clock generation is presented. The proposed ADPLL architecture uses both a digital control mechanism and a ring oscillator and, hence, can be implemented with standard cells. The ADPLL implemented in a 0.3-/spl mu/m one-poly-four-metal CMOS process can operate from 45 to 510 MHz and achieve worst case frequency acquisition in 46 reference clock cycles. The power dissipation of the ADPLL is 100 mW (at 500 MHz) with a 3.3-V power supply. From chip measurement results, the P/sub k/-P/sub k/ jitter of the output clock is <70 ps, and the root-mean-square jitter of the output clock is <22 ps. A systematic way to design the ADPLL with the specified standard cell library is also presented. The proposed ADPLL can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable for system-on-chip applications.

We propose a gain estimation technique of a digital-to-time converter (DTC) and a time-to-digital converter (TDC) intended for an all-digital phase-locked loop (ADPLL) that is based on a recently introduced phase-prediction (PP) technique. Such a PP-ADPLL reduces the timing range and thus complexity of the fractional part of the phase detection mechanism. The conventional TDC gain estimation methods based on measuring the DCO clock period are not feasible for PP-ADPLLs due to the TDC timing range being much smaller than one DCO clock period. The proposed gain estimation method can run concurrently with the normal ADPLL phase locking process and its feasibility is confirmed through behavioral simulations. Although the estimation method is specifically proposed for the PP-ADPLL, its operating principle can also be applied to conventional ADPLL architectures that require an accurate TDC gain estimation.

RETRACTED: A wide range high resolution digital controlled oscillator with high precision time to digital convertor for optimal sampling digital PLL

Dithering scheme has been widely used to improve the resolution of DCO(Digitally Controlled Oscillator) in conventional ADPLLs(All Digital Phase Locked Loop). In this paper a new resolution improvement scheme is proposed where a simple DAC is employed to overcome the problems of dithering scheme. A 2.4GHz LC-based DCO has been designed in a CMOS process with an enhanced frequency resolution for wireless local area network applications. It has a frequency tuning range of 900MHz and a resolution of 58.8Hz. The frequencies are controled by varactors in coarse, fine, and DAC bank. The DAC bank consists of an inversion mode NMOS varactor. The other varactor banks consist of PMOS varactors. Each varactor bank is controlled by 8bit digital signal. The designed DCO exhibits a phase noise of -123.8dBc/Hz at 1MHz frequency offset. The DCO core consumes 4.2mA from 1.2V supply.

This paper describes an ADPLL (All Digital Phase-Locked Loops) with a small DCO (Digitally Controlled Oscillator), low jitter, fine resolution and wide lock range suitable for mobile appplications. The novel DCO circuit is controlled by digital control codes with thermometer type instead of previous binary weighted type. Therefore, the DCO has small area and it has significantly small jitter when the control input is updated. The hierarchical DCO type with two loops makes it possible to have fine resolution and wide lock range. Functional verification and noise analysis of the ADPLL is performed by MATLAB simulink to improve design TAT (Turn-Around Time). And The ADPLL chip is in fabrication using a SEC 0.18 μm CMOS technology. The ADPLL has lock range between 520 MHz and 1.5 GHz and has peak-to-peak jitter 70 ps at 670 MHz.

Digital controlled oscillators (DCOs) are the core of all digital phase locked loop (ADPLL) circuits. Here, DCO structures with reduced hardware and power consumption having full digital control have been proposed. Three different DCO architectures have been proposed based on ring based topology. Three, four and five bit controlled DCO with NMOS, PMOS and NMOS & PMOS transistor switching networks are presented. A three-transistor XNOR gate has been used as the inverter which is used as the delay cell. Delay has been controlled digitally with a switch network of NMOS and PMOS transistors. The three bit DCO with one NMOS network shows frequency variations of 1.6141–1.8790 GHz with power consumption variations 251.9224–276.8591 μW. The four bit DCO with one NMOS network shows frequency variation of 1.6229–1.8868 GHz with varying power consumption of 251.9225–278.0740 μW. A six bit DCO with one NMOS switching network gave an output frequency of 1.7237–1.8962 GHz with power consumption of 251.928–278.998 μW. Output frequency and power consumption results for 4 & 6 bit DCO circuits with one PMOS and NMOS & PMOS switching network have also been presented. The phase noise parameter with an offset frequency of 1 MHz has also been reported for the proposed circuits. Comparisons with earlier reported circuits have been made and the present approach shows advantages over previous circuits.

An all-digital phase locked loop (A-DPLL)-based frequency synthesizer of the local oscillator (LO) for the radio frequency (RF) transceiver application such as in radio frequency identification (RFID) system has gained popularity among academia due to the transition of circuit technology from analog to digital implementation by accessing the benefits in complementary metal-oxide semiconductor (CMOS) process technology. The phase-frequency detector (PFD) is one of the main blocks in ADPLL and it is capable to detect the presence of phase and frequency errors by recognizing two input signals in digital form. The full-ranged of a time-to-digital converter (TDC) is commonly used in PFD block, but the power consumption is high. In this work, the less-TDC will be designed in the digital PFD block as an early development stage design for the ultra-low power ADPLL in order to improve fast phase-frequency acquisition and reduce power consumption. The digital PFD is designed by using Matlab Simulink and Verilog Hardware Description Language (HDL) code. The simulation result obtained that the time difference of the input signals for the Verilog is smaller than the result in Matlab Simulink without a unit delay. Thus, the design of the digital PFD will lead the desired ADPLL to achieve ultra-low power and fast locking range for RFID application.

The previous fast-locked all-digital phase-locked loop (ADPLL) usually suffers from large timing jitter due to the steep frequency transfer curve of its digitally controlled oscillator (DCO). This paper presents an ADPLL that possesses a coarse frequency selection function. All DCO frequency transfer curves of the ADPLL have gentle slopes. The ADPLL selects one transfer curve before acquisition. To fulfill the fast-acquisition requirement, the proposed ADPLL employs the phase–frequency-error compensation technique. In the acquisition mode, the phase-error compensator resolves the problem of phase-error accumulation. Meanwhile, the frequency-error compensator predicts a proper control code by calculating the cycle time difference between the reference clock and the derived signal fed back from the DCO. Therefore, the proposed ADPLL can compensate for the phase and the frequency errors simultaneously. The experimental results show that the proposed ADPLL possesses a fine-tuning acquisition within 5 reference clock cycles. After acquisition, the code updates in a fractional manner in the tracking mode to enhance the tracking jitter performance. The ADPLL output frequency ranges from 860 MHz to 1 GHz. The measured rms jitter is 1.31 ps at 1-GHz frequency.