Demonstration of BEOL-compatible double magnetic tunnel junction pSTT-MRAM devices for low power computing
Rapid advancements in embedded memory technologies have opened the market to a wide range of low power computing applications, such as MCUs and Internet-of-Things (IoT). Innovative solutions, such as Edge computing, where data is stored and processed close to the application, have been proposed as a cost and energy-effective solution. STT-MRAM technology is an attractive candidate for edge computing memory owing to its high endurance (> 1012 cycles), negligible leakage and non-volatility [1-2]. To enable adoption of eMRAM in low power applications, low active power consumption at operating frequencies ≤ 50 MHz is desirable. Reduction in the write power consumption is possible by materials engineering the free and reference layers in conventional MTJ stacks to improve switching characteristics [3, 4] and RA engineering to reduce switching voltages (Vsw) [3]. Unfortunately, Jsw improvement has often come at the cost of a lower Δ, which is unsuitable for the targeted application.An alternative approach to minimizing Jsw is to incorporate two reference layers (RLs) and MgO barriers on either side of the free layer (FL), also known as Double-MTJ (DMTJ) STT-MRAM [4] (Fig. 1a). A critical requirement is the anti-parallel alignment of the RLs which leads to a ‘doubling’ of the total spin torque. However, this approach suffers challenges in processing (two setting fields), TMR performance, RA control, stray field control, degraded retention times and back-end-of-line (BEOL) compatibility [5]. Thus, to demonstrate the feasibility of DMTJ STT-MRAM the following challenges must be addressed: Δ improvement, offset control (μoHoffset < 0.1*μoHc), read/write optimization (TMR>100%, Jsw < 3 MA/cm2), and BEOL compatibility. In this work, we demonstrate device-level performance with full stray field compensation, best-in-class switching (Jsw) and retention (Δ) exceeding 10 years.To achieve BEOL compatibility and compensated stray fields, a 400 °C SAF-SAF design was enabled. Both the bottom-pinned and top-pinned halves of the DMTJ stack employed a synthetic antiferromagnet (SAF) design on either side of the FL. Figure 1(a, b) illustrates the stack design alongside a blanket M-H loop. The challenges involved in the design and demonstration of a 400 °C-compatible top-pinned SAF will be discussed in this work. This includes optimization of the SAF material stack design for annealing and stray field control. The successful demonstration of the SAF-SAF design is shown in the device R-H loops of CD = 80 nm devices where μ0Hoffset ~ 0 mT (Fig. 2a). Figure 2b shows the switching current density (Jsw) trends from 125 devices as a function of pulse-width. An average Jsw = 2.7 MA/cm2 at 50 ns is observed on devices with Δ = 82 kBT and TMR ~ 100%. In addition, WER curves demonstrating 1ppm error-free switching, and a wide switching-breakdown margin of ~0.7 VDC will also be presented. These performance metrics clearly exhibit the importance of the SAF-SAF design in achieving manufacturable DMTJ STT-MRAM devices, thus making it ready for implementation in low power applications. **
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