A digital beamforming receiver architecture implemented on a FPGA for space applications

In digital signal processing, digital down converters (DDCs) convert digitized, band-limited signals to lower frequency signals at a smaller sampling rate to simplify subsequent filtering stages. Software-defined radio (SDR) is a radio communication system in which components that are traditionally implemented in hardware are implemented in software on an embedded system. DDCs are widely used in modern communication systems, such as SDRs. Herein, we propose a low-power- and area-optimized implementation of a DDC for SDR applications. The DDC was designed using an innovative and novel high-level synthesis (HLS) design method based on application-specific bit widths for data nodes. The results achieved after a field programmable gate array (FPGA) implementation are superior to those obtained from hand-coded register transfer level (RTL) implementations in terms of area and power efficiency, with almost the same speed of operation. Our results were obtained using the MATLAB hardware description language (HDL) coder for HLS and Xilinx Vivado (a software for the synthesis and analysis of HDL designs) for synthesis. The DDC down-converts an input of 200 MHz signal to an output of 2 MHz signal. This implementation was conducted on a real FPGA hardware (Xilinx Kintex-7) and verified against the design specifications using an FPGA in the loop feature of HDL Verifier and MATLAB. In addition, we propose a generic methodology for improving the area, speed, and power for different application designs and HLS tools. The proposed methodology is also applicable to hand-coded RTL designs for any application.

Recently, digital Intermediate Frequency (IF) waveform generators and receivers are introduced in modern radar systems to reduce the cost, size, and achieve better performance. Moreover, digital IF waveform generators achieve the requirements of high resolution and complex modulation schemes. Digital receivers have better sensitivity, wider dynamic range and lower noise Figure than analog receivers. Digital IF waveform generators and receivers work well in conjunction with a high-speed Analog to Digital Converters (ADC) and Digital to Analog Converters (DAC). In this paper, the design and implementation of high-speed data acquisition circuits (ADC and DAC) to generate and acquire IF waveforms are presented. Different modulated waveforms are generated digitally using Field Programmable Gate Array (FPGA). The corresponding digital receiver, including digital phase detection and matched filtering, is designed and implemented on the same FPGA chip. Design and implementation of a Printed Circuit Board (PCB) including FPGA chip and its required circuitry are introduced. The proposed design is simulated using Computer-Aided Design (CAD) tools and verified experimentally through laboratory testing.

In this paper, a new architecture is proposed for high-speed Digital Down Conversion (DDC) for communication signal processing. The proposed architecture integrates conventional Polyphase Filter with Polyphase Mixer (PFPM) for decimation in DDC. The PFPM architecture decreases both the rate of the mixer and filter and can process the signals with a very high sample rate, which cannot be realistically implement in conventional DDC in a General Purpose Processor (GPP) such as Field Programmable Gate Array (FPGA) or Digital Signal Processor (DSP). Simulation and experiment have been done to verify the availability of the PFPM architecture. These results show that the proposed PFPM architecture reduces the operation rate of the mixer and well agrees with the conventional DDC architecture.

Nowadays the need for dealing with ultra-high speed Analog to Digital Converter (ADC) is becoming more and more common, from Telecommunications to Precise Instrumentation, every application is increasing the analog to digital interface data rate. The ultra-high sampling rate of the ADCs demands the use of advanced acquisition techniques as well as the latest technology available. The utilization of dedicated Application Specific Integrated Circuit (ASIC) is an expensive solution to deal with the very high throughput from the ADC and its lack of flexibility is a huge drawback. On the other hand, the technology, the architecture and the state-of-the art of the current Field Programmable Gate Arrays (FPGAs) make them especially suitable to act as interface between an ultra-high speed ADC and a data processing unit. Another extra advantage is the reconfigurability of the FPGAs, they can be quickly adapted to different ADCs or different data processing units. The purpose of this paper is to present a practical approach to interface an ultra-high speed 8-bit ADC, MAX104, from Maxim Integrated Circuit, which performs digitalization of the input signal with a sampling rate of 1Gsps and a commercial and popular FPGA, the Virtex2 Pro, from Xilinx Corporation. Once the ADC digital data have been acquired, then they can be processed by either the dedicated FPGA Digital Signal Processing (DSP) blocks, or the FPGA embedded processors or just send the data out to a PC for later processing. Hence, the proposed method of implementation can be used as front-end of a wide range of applications.

Typical radio frequency (RF) digital beamformers can be highly complex. In addition to a suitable antenna array, they require numerous receiver chains, demodulators, data converter arrays, and digital signal processors. To recover and reconstruct the received signal, synchronization is required since the analog-to-digital converters (ADCs), digital-to-analog converters (DACs), field programmable gate arrays (FPGAs), and local oscillators are all clocked at different frequencies. In this article, we present a clock synchronization topology for a multichannel on-site coding receiver (OSCR) using the FPGA as a master clock to drive all RF blocks. This approach reduces synchronization errors by a factor of 8, when compared to conventional digital beamformer.

Usage of digital receivers in today's radar and electronic warfare applications is becoming more common. Analog to digital converters (ADC) used in digital receivers play a significant role in the performance of these receivers. Therefore, it is very important to obtain performance analysis of possible ADC's under different conditions such as different temperature etc. before making final decision of the ADC to be used in the digital receiver. It is obvious that it would be very helpful to get results of integration of different ADC's with the existing system and to test ADC's under different conditions that may not exist on data sheets. For this reason, a Field Programmable Gate Array (FPGA) based board is designed in order to gather digital output of ADC being evaluated and a graphical analysis software responsible for analyzing gathered digital output is developed. Developed infrastructure enables us to compare performances of different ADC's in the same system and in same conditions by replacing only the ADC to be analyzed.

This paper introduces a field-programmable gate array (FPGA)-based digital down converter (DDC) processing a sampling frequency of about 3.64 GHz to a down-converted frequency of 28.4375 MHz to match the IEEE 802.11ah Wi-Fi HaLow standard. The proposed DDC uses a polyphase mixer(PM) and a resampling filter. The PM adopts parallel coordinate rotation digital computer (CORDIC) processors and lowpass filter arrays to reduce high-speed data rates with minimum resource utilization. Again, the resampling filter employs a cascaded integrator comb (CIC) filter associated with a parallel prefixed adder (PPA) and a multi-channel systolic finite impulse response (FIR) filter implemented with canonical expression, attaining optimum hardware cost. Converting floating-point to fixed-point data types provides significant resource savings. Finally, the improved design is coded in the Xilinx Vivado synthesis tool and successfully tested on the FPGA Kintex-7 device. In contrast to other recent architectures, the proposed design substantially reduces area requirements and power utilization. The Matlab tool verifies the design to achieve an acceptable spurious-free dynamic range (SFDR) of 115 dB.

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The use of an automated Data Acquisition System (DAS) is very important in testing and measurement systems. The desire is extremely high in the DAS with high speed, multi-channel, and large capacity, so research in this area becomes very significant. The growing problem in DAS is to acquire the data with the required data rate and store data onto the on-chip memory. Microcontroller, microprocessor or Digital Signal Processors (DSP) devices can be programmed as a DAS, but these devices comprise problems, such as slower data acquisition rates, nonavailability of sufficient on-chip memory, etc. To overcome these above drawbacks, this paper provides an approach to design and develop DAS based on the Field Programmable Gate Array (FPGA). To acquire the data from Analog to Digital Converter (ADC) to FPGA, an Inter Integrated Circuit (I2C) serial communication protocol is used. I2C master communication protocol is designed and developed using VHDL with the Quartus II version 13.1, and the I2C master protocol is implemented in cyclone III FPGA. FPGA is acting as a master controller. DAS with the FPGA will provide the better acquisition results compared to the existing acquisition system.

Motion estimation in videos is a computationally intensive process. A popular strategy for dealing with such a high processing load is to accelerate algorithms with dedicated hardware such as graphic processor units (GPU), field programmable gate arrays (FPGA), and digital signal processors (DSP). Previous approaches addressed the problem using accelerators together with a general purpose processor, such as acorn RISC machines (ARM). In this work, we present a co-processing architecture using FPGA and DSP. A portable platform for motion estimation based on sparse feature point detection and tracking is developed for real-time embedded systems and smart video sensors applications. A Harris corner detection IP core is designed with a customized fine grain pipeline on a Virtex-4 FPGA. The detected feature points are then tracked using the Lucas---Kanade algorithm in a DSP that acts as a co-processor for the FPGA. The hybrid system offers a throughput of 160 frames per second (fps) for VGA image resolution. We have also tested the benefits of our proposed solution (FPGA + DSP) in comparison with two other traditional architectures and co-processing strategies: hybrid ARM + DSP and DSP only. The proposed FPGA + DSP system offers a speedup of about 20 times and 3 times over ARM + DSP and DSP only configurations, respectively. A comparison of the Harris feature detection algorithm performance between different embedded processors (DSP, ARM, and FPGA) reveals that the DSP offers the best performance when scaling up from QVGA to VGA resolutions.

This paper designs a novel hybrid (a mixture of analog and digital) beamforming and examines the relation between the hybrid and digital beamformings for downlink multiuser massive multiple input multiple output (MIMO) systems. We assume that perfect channel state information is available only at the transmitter and we consider the total sum rate maximization problem. For this problem, the hybrid beamforming is designed indirectly by considering a weighed sum mean square error (WSMSE) minimization problem incorporating the solution of digital beamforming which is obtained from the block diagonalization technique. The resulting WSMSE problem is solved by applying the theory of compressed sensing. The relation between the hybrid and digital beamformings is studied numerically by varying different parameters, such as the number of radio frequency (RF) chains, analog to digital converters (ADCs) and multiplexed symbols. Computer simulations reveal that for the given number of RF chains and ADCs, the performance gap between digital and hybrid beamformings can be decreased by decreasing the number of multiplexed symbols. Moreover, for the given number of multiplexed symbols, increasing the number of RF chains and ADCs will increase the total sum rate of the hybrid beamforming which is expected.

Radio frequency (RF) systems in space applications are usually designed for a single task and its requirements. Flexibility is mostly limited to software-defined adaption of the signal processing in digital signal processors (DSP) or field-programmable gate arrays (FPGA). RF specifications, such as frequency band selection or RF filter bandwidth are thereby restricted to the specific application requirements. New radio frequency integrated circuit (RFIC) devices also allow the software-based reconfiguration of various RF specifications. A transfer of this RFIC technology to space systems would have a massive impact to future radio systems for space applications. The benefit of this RFIC technology allows a selection of different RF radio applications, independent of their RF parameters, to be executed on a single unit and, thus, reduces the size and weight of the whole system. Since most RF application sin space system require a high level of reliability and the RFIC is not designed for the harsh environment in space, a characterization under these special environmental conditions is mandatory. In this paper, we present the single event effect (SEE) characterization of a selected RFIC device under proton irradiation. The RFIC being tested is immune to proton induced single event latch-up and other destructive events and shows a very low response to single failure interrupts. Thus, the device is defined as a good candidate for future, highly integrated radio system in space applications.

The evaluation of ultrasound system is measured by the development in analog and digital electronics. A modular field programmable gate array (FPGA)-based digital ultrasound beamforming is presented. The digital beamforming is implemented in Virtex-5 FPGA. The objective of this work is to develop a modular low-cost PC-based digital ultrasound imaging system that has almost all of its processing steps done on the PC side. The system consists of: two 8 channels block and reconstructed line block. The 8 channel block consist of: memory block to save the samples data after converted to fixed point type, delay block implemented by addressable shift register — the delay process is based on sampled delay focusing (SDF) — and M-code block applied the summation of each RF channel samples. The reconstructed block consists of pipelined adder to apply the summation of the two 8 channels blocks. The power consumption and device utilization was acceptable. Also it is possible to build 16-,32-,64-, and 128-channel beamformer. The hardware architecture of the design provided flexibility for beamforming.

Digital Down Conversion (DDC) is a fundamental process in software defined radio (SDR) and digital communications, which transforms intermediate frequency (IF) signals into baseband signals. In conventional DDC designs, multipliers and look-up tables are generally employed, both of which tend to increase hardware size and power consumption. In this paper we present a Dual-Mode CORDIC-Based DDC architecture which uses the CORDIC (Coordinate Rotation Digital Computer) algorithm to eliminate multipliers. This novel architecture combines a CORDIC-based Numerically Controlled Oscillator (NCO), a CORDIC mixer, and a Cascaded Integrator-Comb (CIC) filter with a finite impulse response (FIR) com pentation filter. The NCO provides two precision modes - an 8-stage low-latency mode for speed and a 16-stage high precision mode for accuracy, giving runtime reconfigurability according to design requirements. Simulations and analysis show that the design gives highly accurate frequency translation, is efficient in hardware utilization and fully eliminates the use of digital signal processing (DSP) blocks. Overall, the architecture proposed offers a low-power, low-cost, and recon figural solution ideal for modern SDR-based applications and flexible digital signal processing systems.

Present days witnessed extensive use of Analog to Digital Converters (ADC) in different fields of applications, as an interface between the analog world and the digital world. However, in most cases, external ADCs are employed to meet the purpose. This eventually makes the system bulky, power-consuming, complex, and costly. Implementation of reconfigurable ADC programmed inside Field-Programmable Gate Array (FPGA) could reduce the system cost and power consumption substantially. Furthermore, this will make the system simple as it does not require any external circuitry for the conversion of analog input data into digital form for processing. Thus, in this paper, a multichannel reconfigurable ADC is designed, with an additional feature of time multiplexing for efficient data acquisition. The design is being implemented using 100MHz FPGA clock frequency thus can achieve a sampling rate of 100 MS/s with a resolution of 10bit for 0-2.5V signal range. The FPGA resource utilization for the complete ADC model consists of 341 FFs and 265 LUTs, with total on-chip power consumption of 14.428 W. The proposed system can also be implemented for different analog signal from transducers, depending upon the demand and requirement of sensing parameters the data collection time can be varied for transducer to transducer.