A Dynamic Operational Semantics for JVML.

A local approach for temporal model checking of Java bytecode

Dataflow languages allow the specification of reactive systems by mutually recursive stream equations, functions, and boolean activation conditions called clocks. Lustre and Scade are dataflow languages for programming embedded systems. Dataflow programs are compiled by a succession of passes. This article focuses on the normalization pass which rewrites programs into the simpler form required for code generation. Vélus is a compiler from a normalized form of Lustre to CompCert’s Clight language. Its specification in the Coq interactive theorem prover includes an end-to-end correctness proof that the values prescribed by the dataflow semantics of source programs are produced by executions of generated assembly code. We describe how to extend Vélus with a normalization pass and to allow subsampled node inputs and outputs. We propose semantic definitions for the unrestricted language, divide normalization into three steps to facilitate proofs, adapt the clock type system to handle richer node definitions, and extend the end-to-end correctness theorem to incorporate the new features. The proofs require reasoning about the relation between static clock annotations and the presence and absence of values in the dynamic semantics. The generalization of node inputs requires adding a compiler pass to ensure the initialization of variables passed in function calls.

Exception handling method and apparatus for a microkernel data processing system

Over recent years, various semantics have been proposed for dealing with updates in the setting of logic programs. The availability of different semantics naturally raises the question of which are most adequate to model updates. A systematic approach to face this question is to identify general principles against which such semantics could be evaluated. In this paper we motivate and introduce a new such principle – the refined extension principle – which is complied with by the stable model semantics for (single) logic programs. It turns out that none of the existing semantics for logic program updates, even though based on stable models, complies with this principle. For this reason, we define a refinement of the dynamic stable model semantics for Dynamic Logic Programs that complies with the principle.

Stephen J. Hartley Oxford University Press, New York, 1998, 260 pp. ISBN 0-19-511315-2, $45.00 Concurrent Programming is a thorough treatment of Java multi-threaded programming for both a stand-alone and distributed environment. Designed mostly for students in concurrent or parallel programming classes, the text is also an excellent reference for the practicing professional developing multi-threaded programs or applets. Hartley first provides a complete explanation of the features of Java necessary to write concurrent programs, including topics such as exception handling, interfaces, and packages. He then gives the reader a solid background to write multi-threaded programs and also presents the problems introduced when writing concurrent programs—namely race conditions, mutual exclusion, and deadlock. Hartley also provides several software solutions that do not require the use of common process and thread mechanisms. Once the groundwork is laid for writing concurrent programs, Hartley then takes a different approach than most Java references. Rather than presenting how Java handles mutual exclusion with the synchronized keyword (although it is covered later), he first looks at semaphore-based solutions to classic concurrent problems such as bounded-buffer, readers-writers, and the dining philosophers. Hartley also uses the same approach to develop Java classes for monitors and message passing. This unique approach to introducing concurrency allows the readers to both understand how Java threads are synchronized and how the basic synchronization mechanism can be used to construct more abstract tools such as semaphores. If there is a shortcoming with the text it is with the lack of sufficient coverage of remote method invocation (RMI), although there is a section covering RMI. This is quite understandable as RMI is a fairly recent phenomenon with the Java community. Also, the classes that Hartley provides could easily implement RMI rather than sockets to handle communication. The strengths of the book include its ease in reading, several examples at the end of chapters, a package similar to Xtango that provides algorithm animation, and a supportive web site by the author (see www.mcs.drexel.edu/~shartley/ConcProgJava/index.html ) including compressed source code. As Java becomes more dominant on the server side of multi-tier applications, writing thread-safe concurrent applications becomes even more important. Concurrent Programming is a strong step towards teaching students and professionals such skills. Greg Gagne, Westminster College of Salt Lake City Salt Lake City, Utah

: RED is a programmed language designed, in accordance with the DOD steelman requirements, for DoD embedded computer applications. The language combines features common to most existing high level languages with new capabilities for abstract data types, exception handling, multitasking, generic definitions and access to machine-dependent facilities. This manual covers lexical structures, program structures, types, expression, statements, procedures, functions and parameters, capsules, exception handling, multitasking, overloading and generics, machine dependent facilities, advanced definitions, and low level facilities. The RED language has been designed to reduce the total life cycle cost of designing, implementing, testing, and maintaining programs. For small and medium size programs, most modern high level languages are similar. However, for large programs, such as those commonly developed for embedded applications, the facilities provided by a language become crucial. What distinguishes the RED language is that it makes it easy to express solutions to the problems encountered when developing large programs.

The tremendous computing power of Graphics Processing Units (GPUs) can be used to accelerate the evolution process in Genetic Programming (GP). The automatic generation of code using the GPU usually follows two different approaches: compiling each evolved or interpreting multiple programs. Both approaches, however, have performance drawbacks. In this work, we propose a novel approach where the GPU pseudo-assembly language, PTX (Parallel Thread Execution), is evolved. Evolving PTX programs is faster, since the compilation of a PTX program takes orders of magnitude less time than a CUDA program compilation on the CPU, and no interpreter is necessary. Another important aspect of our approach is that the evolution of PTX programs follows the Quantum Inspired Linear Genetic Programming (QILGP). Our approach, called QILGP3U (QILGP + GPGPU), enables the evolution on a single machine in a reasonable time, enhances the quality of the model with the use of PTX, and for big databases can be much faster than the CPU implementation.

Decomposing software according to the structure of the problem domain makes it easier to manage its complexity. Such a decomposition requires a programming language that supports compositions matching those in the problem domain. However, current programming languages only offer a restricted set of control-flow related composition mechanisms, such as method invocation and exception handling. This limits developers in choosing the desired decomposition. Previously, we showed that continuations are suitable for implementing various control-flow compositions. However, composing and refining these implementations requires new language features. In this paper, we outline requirements for control-flow composition and show how exception handling can be implemented using continuations, scopes and bindings.

A comparative study of exception handling mechanisms for building dependable object-oriented software

In most multithreaded node architectures moti- vated by the dataflow computational model, spatial parallelism could not be exploited at the thread level due to the resource deficit incurred by their inter nal organization. So we proposed a node architecture exploiting both spatial and temporal parallelism of a program. A multi-port non-blocking data cache is in corporated into our design to cope with the excessive data bandwidth required in parallel execution of mul tiple threads. The proposed node architecture may contribute to greatly reducing communication latency through the interconnection network. Simulation re sults show that parallel loops can be executed on this architecture more efficiently than on other competi tive ones.

Semantic web Racer: Dynamic security testing of the web application against race condition in the business layer

Before a PV module is integrated into a PV system it has to be handled and transported. This handling and transport is a critical stage of the PV-modules life. In order to identify critical handling steps we accompanied the installation of PV systems and compiled a list of typical and exceptional handling situations. From these observations we developed test to be performed in the laboratory. The tests are designed to account for the mechanical installation conditions as well as for the module temperature during the installation. As a result we find that the most critical handling step is the lay down of the PV module with sunny side up. During the lay down of the module one might let drop the module on one side from a low height. For one module type we found even for a 5 cm drop height more than 5 cracked cells after the drop. In contrast a vertical drop of a framed PV module results in no cell breakage at all. Additionally the risk of cell breakage rises for static loads by at least factor two with PV module temperature of -5°C compared to 25°C. Therefore one should avoid installing PV modules below the freezing point.

The era of Heterogeneous systems and Big Data computing is already here. Handling huge amount of data poses new challenges in data management and in the effective usage of memory, caches, heterogeneous structures and available bandwidth. In addition, computing requirements of Big Data is unique; in many occasions the processing required per storage access is limited (i.e. low Instructions/Byte) which presents a new challenge and opportunities for computer architects. The increasing performance requirement are driving the industry towards parallel execution of threads (or tasks) being executed by energy efficient computing (e.g. heterogeneous) engines. In this talk well present some of the research being performed at the Technion, which is related to effective usage of caches and heterogeneous systems in multiasking environment and will provide a scent of remedy to the situation. In addition we will present the substantial issue of non-temporal-memory-access in Big Data environment and suggest some hopefully stimulating solutions.

A future is a well-known programming construct used to introduce concurrency to sequential programs. Computations annotated as futures are executed asynchronously and run concurrently with their continuations. Typically, futures are not transparent annotations: a program with futures need not produce the same result as the sequential program from which it was derived. Safe futures guarantee a future-annotated program produce the same result as its sequential counterpart. Ensuring safety is especially challenging in the presence of constructs such as exceptions that permit the expression of non-local control-flow. For example, a future may raise an exception whose handler is in its continuation. To ensure safety, we must guarantee the continuation does not discard this handler regardless of the continuation’s own internal control-flow (e.g. exceptions it raises or futures it spawns). In this paper, we present a formulation of safe futures for a higher-order functional language with first-class exceptions. Safety can be guaranteed dynamically by stalling the execution of a continuation that has an exception handler potentially required by its future until the future completes. To enable greater concurrency, we develop a static analysis and instrumentation and formalize the runtime behavior for instrumented programs that allows execution to discard handlers precisely when it is safe to do so.

Modern Graphic Processing Units (GPUs) provide sufficiently flexible programming models that understanding their performance can provide insight in designing tomorrow's manycore processors, whether those are GPUs or otherwise. The combination of multiple, multithreaded, SIMD cores makes studying these GPUs useful in understanding tradeoffs among memory, data, and thread level parallelism. While modern GPUs offer orders of magnitude more raw computing power than contemporary CPUs, many important applications, even those with abundant data level parallelism, do not achieve peak performance. This paper characterizes several non-graphics applications written in NVIDIA's CUDA programming model by running them on a novel detailed microarchitecture performance simulator that runs NVIDIA's parallel thread execution (PTX) virtual instruction set. For this study, we selected twelve non-trivial CUDA applications demonstrating varying levels of performance improvement on GPU hardware (versus a CPU-only sequential version of the application). We study the performance of these applications on our GPU performance simulator with configurations comparable to contemporary high-end graphics cards. We characterize the performance impact of several microarchitecture design choices including choice of interconnect topology, use of caches, design of memory controller, parallel workload distribution mechanisms, and memory request coalescing hardware. Two observations we make are (1) that for the applications we study, performance is more sensitive to interconnect bisection bandwidth rather than latency, and (2) that, for some applications, running fewer threads concurrently than on-chip resources might otherwise allow can improve performance by reducing contention in the memory system.