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  • https://doi.org/10.1109/iscas.2017.8050317Copy DOI Icon

A fast FPGA-based deep convolutional neural network using pseudo parallel memories

  • May 1, 2017
  • Muluken Hailesellasie +1 more
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Abstract

Deep learning is gaining popularity in the recent years due to its impressive performance in different application areas. Convolutional Neural Network (CNN) is the state-of-the-art deep learning architecture that is being used widely in the areas of image recognition, speech recognition and many other applications. CNN is computationally intensive and resource hungry architecture. Hence, its efficient hardware implementation is one of the challenges faced by researchers. FPGAs are the dominating platform choice when it comes to implementation of such architectures. This paper presents an efficient implementation of convolutional layer of CNN, that can substantially reduce the long computational time by utilizing the parallel usage of memories. The technique proposed distributes the input image to be classified into P memories; where P is obtained as an optimum trade-off between number of clock cycles and memory resources. Reading concurrently from all P memories reduces the required number of clock cycles proportionally, at the expense of complex control unit. The proposed architecture is implemented using Xilinx Vivado, targeting Zynq XC7Z020-1CLG484C device. The architecture is tested using MNIST dataset and successfully compared with Caffe's convolutional layer output.

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