A Fast Iterative Method for Solving the Eikonal Equation on Triangulated Surfaces

SIMD (Single Instruction Multiple Data) architectures are widely used in application domains like the wireless communication, video and audio processing, and control engineering. The abundant data parallelism makes the SIMD architecture the proper match in data processing and performance improvement. However, there are also critical inefficiencies in current SIMD architectures. To understand such inefficiency, we carry out a deep investigation in the main components of Long Term Evolution (LTE) protocol, which is an important wireless communication protocol. Performance investigation is taken on a cycle-accurate simulator, featuring the main characteristics of existing SIMD architectures. Based on the investigation, we locate the inefficiencies in two aspects: the data communication operations among different processing units and the support for matrix-style computations. We have also carried out studies with enhanced SIMD architectures in the above two aspects. The overall performance of SIMD architectures can be greatly improved.

Due to the high computational complexity of the full-search algorithm for video coding, techniques to accelerate the execution of the full-search algorithm are needed for real-time implementations of current video compression standards. In this paper, a technique of using eight-bit partial sums of four luminance values is proposed to reduce the computational complexity of the original full-search algorithm without loss of its accuracy. Furthermore, since the proposed technique is suitable for the implementation on the single instruction multiple data (SIMD) architectures, the byte-type data-parallelism of the SIMD architecture can be utilized to further accelerate the execution of the proposed technique. Simulation results for the benchmark video test sequences demonstrate that the proposed technique can significantly accelerate the execution of the full-search algorithm on SIMD architectures without loss of its accuracy.

Among all the existing methods to solve the eikonal equation, three methods are chosen to verify accuracy, symmetry, reciprocity and error propagation along large offsets of refracted waves in seismic near surface exploration context. Performance is extremely highlighted nowadays and accuracy is being neglected, then an eikonal solver poorly explored in geoscience is used. A classical solver, the Fast Iterative and the modified Fast Sweeping Method are applied in three modeling schemes: a simple two layers model, a large four layers and a complex benchmark model. The three methods compute the first arrival of refracted waves in high contrast media and the results are compared to the analytical solution. A circular geometry is considered in all experiments to explore the method applicability using full azimuth angles. On the first scheme, the errors in travel time are computed among the three methods using different model sample spacing and we discuss accuracy, symmetry and reciprocity of first arrivals. On the second scheme, three circular receivers are placed in different offsets to check errors along refracted wave propagation. Finally, the third scheme, four shots are strategically positioned over the SEG/EAGE Overthrust model in order to compare the full acoustic wavefield with the eikonal solvers and then check the similarities. Although the focus is on methods accuracy, the algorithm run time is also considered and the comparison shows that the modified Fast Sweeping Method is the most accurate. The most computational efficient eikonal solver is the Fast Iterative Method, but its geoscience applicability needs to be cautious, because of its inaccurate results.

Fast Iterative Method in Solving Eikonal Equations: A Multi-level Parallel Approach

Energy efficiency has become one of the most important topics in computing. To meet the ever increasing demands of the mobile market, the next generation of processors will have to deliver a high compute performance at an extremely limited energy budget. Wide single instruction, multiple data (SIMD) architectures provide a promising solution, as they have the potential to achieve high compute performance at a low energy cost. We propose a configurable wide SIMD architecture that utilizes explicit datapath techniques to further optimize energy efficiency without sacrificing computational performance. To demonstrate the efficiency of the proposed architecture, multiple instantiations of the proposed wide SIMD architecture and its automatic bypassing counterpart, as well as a baseline RISC processor, are implemented. Extensive experimental results show that the proposed architecture is efficient and scalable in terms of area, performance, and energy. In a 128-PE SIMD processor, the proposed architecture is able to achieve an average of 206 times speed-up and reduces the total energy dissipation by 48.3 % on average and up to 94 %, compared to a reduced instruction set computing (RISC) processor. Compared to the corresponding SIMD architecture with automatic bypassing, an average of 64 % of all register file accesses is avoided by the 128-PE, explicitly bypassed SIMD. For total energy dissipation, an average of 27.5 %, and maximum of 43.0 %, reduction is achieved.

We present a family of fast and accurate Dijkstra-like solvers for the eikonal equation and factored eikonal equation which compute solutions on a regular grid by solving local variational minimization problems. Our methods converge linearly but compute significantly more accurate solutions than competing first order methods. In 3D, we present two different families of algorithms which significantly reduce the number of FLOPs needed to obtain an accurate solution to the eikonal equation. One method employs a fast search using local characteristic directions to prune unnecessary updates, and the other uses the theory of constrained optimization to achieve the same end. The proposed solvers are more efficient than the standard fast marching method in terms of the relationship between error and CPU time. We also modify our method for use with the additively factored eikonal equation, which can be solved locally around point sources to maintain linear convergence. We conduct extensive numerical simulations and provide theoretical justification for our approach. A library that implements the proposed solvers is available on GitHub.

The aim of this study is to present the steps of optimization the H.264 / AVC video decoder for MIPS32 DSP ASE SIMD (Single-instruction, multiple-data) processor architecture. In particular, SIMD architecture can be very efficient in the implementation of video applications which have simple operations on 8-bit or 16-bit samples. Besides already mentioned architecture it is also important to get familiar with the H.264 / AVC video code standards. The parts of decoder that were subject of optimization were detected as the biggest consumers of CPU resources. After optimization, overall system speedup gain was 36%.

Biofluids, like urine, form very complex matrixes containing a large number of potential biomarkers, that is, changes of endogenous metabolites in response to xenobiotic exposure. This paper describes a fast and sensitive method of screening biomarkers in rat urine. Biomarkers for phospholipidosis, induced by an antidepressant drug, were studied. Urine samples from rats exposed to citalopram were analyzed using solid-phase extraction (SPE) and liquid chromatography mass spectrometry (LC/MS) analysis detecting negative ions. A fast iterative method, called Gentle, was used for the automatic curve resolution, and metabolic fingerprints were obtained. After peak alignment principal component analysis (PCA) was performed for pattern recognition, PCA loadings were studied as a means of discovering potential biomarkers. In this study a number of potential biomarkers of phospholipidosis in rats are discussed. They are reported by their retention time and base peak, as their identification is not within the scope of the study. In addition to the fact that it was possible to differentiate control samples from dosed samples, the data were very easy to interpret, and signals from xenobiotic-related substances were easily removed without affecting the endogenous compounds. The proposed method is a complement or an alternative to NMR for metabolomic applications.

Dzięki upowszechnieniu się procesorów wielordzeniowych przetwarzanie danych za pomocą obliczeń równoległych staje się coraz bardziej dostępne dla szerokiego grona użytkowników. Przykładem jest opracowana przez firmę NVIDIA architektura CUDA, będąca architekturą wielordzeniowych procesorów graficznych. Procesor graficzny może być traktowany jako procesor SIMD z pamięcią wspólną. Na przykładzie operacji mnożenia macierzy zbadano wpływ zarządzania pamięcią i blokami wątków na czas obliczeń z użyciem architektury CUDA.

Pre-corrected Tensor Train (P-TT) fast iterative method is introduced for acceleration of Method of Moments (MoM) solution of the 2D Volume Electric Field Integral Equation (V-EFIE) in magneto-quasi-static regime. The method performs voxelization of the unstructured triangle mesh in MoM discretization through projection of the basis and test functions onto the regular grid of point sources. Subsequently, the Toeplitz matrix governing point-to-point interactions is represented as multi-dimensional tensor and decomposed into the product of smaller dimensional tensors (Tensor Train (TT)). The storage of the TT carriages and vectors pertinent to P-TT requires O(log N) and O(N) memory, respectively. Evaluation of the matrix-vector product requires O(N log N) operations. Resistance and inductance of the circular wire are extracted in broad range of frequencies with proposed P-TT algorithm and compared against analytical values.

The use of a wide Single-Instruction-Multiple-Data (SIMD) architecture is a promising approach to build energy-efficient high performance embedded processors. In this paper, based on our design framework for low-power SIMD processors, we propose a multiply-accumulate (MAC) unit with variable number of accumulator registers. The proposed MAC unit exploits both the merits of merged operation and register tiling. A Convolutional Neural Network (CNN) is a popular learning based algorithm due to its flexibility and high accuracy. However, a CNN-based application is often computationally intensive as it applies convolution operations extensively on a large data set. In this work, a CNN-based intelligent learning application is analyzed and mapped in the context of SIMD architectures. Experimental results show that the proposed architecture is efficient. In a 64-PE instance, the proposed SIMD processor with MAC4reg achieves an effective performance of 63.2 GOPS. Compared to the two baseline SIMD processors without MAC4reg, the proposed design brings 54.0% and 32.1% reduction in execution time, and 20.5% and 35.1% reduction in energy consumption respectively.

The general-purpose neural network processor is designed for the most neural networks algorithm and is required for variable bit length data processing ability. This paper proposes a processor that is based on SIMD (Single Instruction Multiple Data) architecture with three data bit mode: 8-bit, 16-bit and 32-bit. It can use the memory and ALU sufficiently when the bit mode changes. The processor is designed basing on 0.25–micron process technology and it can be synthesized at 50MHz with PKS of Cadence Inc. The experiment result shows that the processor can implement the neural network in highly parallel.KeywordsLogic ModuleExtreme Learn MachineHardware ImplementationRegister FileTime SpendingThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Existing fault simulation techniques have a worst-case computational complexity of O(n**2), where n is the number of devices in the circuit. A parallel hardware accelerated fault simulator (PHAFS) has been proposed in order to reduce the complexity to O(L**2), where L is the number of levels of switches encountered when traversing from output to input. An overview of the PHAFS architecture and system is presented. The PHAFS hardware component uses a massively parallel SIMD (single instruction, multiple data) architecture based on an application specific integrated circuit to perform two-dimensional parallel switch level fault simulation up to 32 switches and 192 faults. >

Computer simulation of materials using parallel architectures

Software defined radio (SDR) systems require programmable architectures that provide high performance combined with high energy efficiency. Wide single instruction, multiple data (SIMD) architectures could potentially satisfy these demands, but only few publications examine the interdependence between the SIMD width and the performance of typical SDR algorithms. In this paper, we present a detailed analysis of three SDR algorithm classes on a newly developed scalable SIMD architecture, which combines SIMD processing with long instruction word (LIW) execution. Although radix-2 and mixed-radix fast Fourier transform, sphere decoding, and low-density parity-check decoding all benefit from SIMD processing, our results show that there are different constraints on the performance.