A frequency steered phase locked loop

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

CMOS phase-locked loops (PLL) are ubiquitous in RF and mixed-signal integrated circuits. PLLs are very sensitive to noise fluctuations on the power and ground rails. In this paper, a general comprehensive stochastic model of the power/ground (P/G) noise in VLSI circuits is presented. This is followed by calculation of the phase noise of the voltage-controlled oscillator (VCO) in terms of the statistical properties of supply noise. The PLL timing jitter is predicted in response to the VCO phase noise. Next, the design of a low power, 2.5 V, 0.25 /spl mu/ CMOS PLL clock generator with a lock range of 100 MHz-400 MHz is described. Our mathematical method is utilized to study the jitter-induced P/G noise in this PLL. A comparison between the results obtained by our mathematical model and those obtained by HSPICE simulation prove the accuracy of the predicted model.

This paper presents a detailed analysis of PLL structures for utility connected systems. The three-phase PLL (phase-locked loop) structure capable of fast tracking the utility voltage vector is studied. A single-phase PLL structure, derived from the three-phase PLL topology, is discussed and its behavior under distorted utility conditions is analyzed. Additionally, the conventional zero-crossing PLL is studied and an alternative implementation for this PLL is proposed in order to improve its dynamic behavior. Simulation and experimental results from a DSP-based system are included to support the theoretical analysis.

Phase Locked Loop (PLL) circuit plays an important part in electronic communication system in providing high-frequency clock, recovering the clock from data signal and so on. The performance of PLL affects the whole system. As the frequency of PLL increases, designing a PLL circuit with lower jitter and phase noise becomes a big challenge. To suppress the phase noise, the optimization of Voltage Controlled Oscillator (VCO) is very important. As the power supply voltage degrades, the VCO becomes more sensitive to supply noise. In this work, a three-stage feedforward ring VCO (FRVCO) is designed and analyzed to increase the output frequency. A novel supply-noise sensing (SNS) circuit is proposed to suppress the supply noise’s influence on output frequency. Based on these, a 1.2 V 2 GHz PLL circuit is implemented in 110 nm CMOS process. The phase noise of this CMOS charge pump (CP) PLL is 117 dBc/Hz@1 MHz from test results which proves it works successfully in suppressing phase noise.

This paper describes a low spurious and small step frequency synthesizer module based on PLL (Phase-Locked Loop)-DDS (Direct Digital Synthesis)-PLL structure, which is controlled by the parallel port of the computer. The module consists of four parts: the first PLL (PLL1), the DDS, the second PLL (PLL2) and the control part. The spurious of this module is ameliorated to some extent in comparison with traditional synthesizer technologies using single PLL. The experimental measurement of the actual module shows that the spurious is as low as -65 dBc. In addition, its frequency range is 2060 MHz-2160 MHz, the frequency step size 10 kHz, the phase noise -90 dBC/Hz@10 kHz and the harmonics -40 dBc.

This paper presents a novel combination of two fully integrated phase-locked loops (PLLs) to control the oscillation frequency and modulation frequency of a switched injection-locked oscillator (SILO). The SILO is used as an active reflector transponder in a frequency-modulated continuous wave (FMCW) radar system. A fractional-N PLL (RF-PLL) with a tri-state phase-frequency detector (TSPFD) sets the oscillation frequency of the voltage controlled oscillator (VCO) to 2.45 GHz. Another integer-N PLL (modulation PLL) switches the tail current source of the VCO to achieve SILO behavior at the time when the RF-PLL is not controlling the VCO. The RF-PLL supports division ratios from 64 to 511 with a frequency resolution of 0.2 Hz. Reference spur levels are below -48 dBc while the out-of-band phase noise is -103 dBc/Hz at a 1MHz frequency offset. The modulation PLL is based on a Maneatis-cell ring-oscillator supporting modulation frequencies between 6MHz and 20 MHz. Furthermore, the duty cycle of the modulation signal can be set in steps of 0.8 %. Due to the novel TSPFD, the oscillation frequency of the SILO changes only by 36MHz within 10 minutes when the RF-PLL is inactive. The complete circuit is manufactured in a 180nm SiGe BiCMOS process and consumes a total power of 128mW.

Many of today's applications require that a phase-locked loop (PLL) operate at high speeds, while maintaining reasonable phase noise and jitter performance. Voltage-controlled oscillators (VCO) are important building blocks in PLLs. More importantly, the VCO is the major contributor of phase noise in a PLL. The noisy environment, mainly due to the switching noise generated by the digital portion of these systems. imposes stringent constraints on the design of VCOs, especially phase noise or timing jitter. The switching noise originated in the digital portion of the systems are coupled to the supply and ground rails of the VCO of PLLs. Another important block of a PLL is the charge-pump, a block that is responsible for generating the control voltage to be applied to the VCO. The stability or fluctuation of the control voltage, can severely affect the phase noise performance of the VCO. The research in this thesis, centered on (i) the design considerations of CMOS charge-pumps, (ii) the timing jitter of the delay-cells of low-voltage CMOS ring-VCOs and (iii) the design of a high-speed ring oscillator. A PLL was designed using a new active inductor 6.3-GHz ring oscillator, with a tuning range of +/- 15% was designed in 0.18um CMOS technology. The ring oscillator employed active inductor loads that resulted in an improvement of about 42% in oscillation frequency when compared to the conventional resistor loaded ring oscillator.

In most grid-connected power converter applications, the phase-locked loop (PLL) is probably the most widespread grid synchronization technique, owing to its simple implementation. However, its phase-tracking performance tends to worsen when the grid voltage is under unbalanced and distorted conditions. Many filtering techniques are utilized to solve this problem, however, at the cost of slowing down the transient response. It is a major challenge for PLL to achieve a satisfactory dynamic performance without degrading its filtering capability. To tackle this challenge, a hybrid filtering technique is proposed in this paper. Our idea is to eliminate the fundamental frequency negative sequence (FFNS) and other harmonic sequences at the prefiltering stage and inner loop of PLL, respectively. Second-order generalized integrators (SOGIs) are used to remove FFNS before the Park transformation. This makes moving average filters (MAFs) eliminate other harmonics with a narrowed window length, which means the time delay that is caused by MAFs is reduced. The entire hybrid filtering technique is included in a quasi-type-1 PLL structure (QT1-PLL), which can provide a rapid dynamic behavior. The small-signal model of the proposed PLL is established. Based on this model, the parameter design guidelines targeting the fast transient response are given. Comprehensive experiments are carried out to confirm the effectiveness of our method. The results show that the settling time of the proposed PLL is less than one grid cycle, which is shorter than most of the widespread PLLs. The harmonic rejection capability is also better than other methods, under both nominal and adverse grid conditions.

This study was devoted to oscillator noise analysis and simulation in order to apply it on VCOs (Voltage Controlled Oscillator) for Intermediate Frequency integrated circuits, especially for TV receivers. An original period jitter transient simulation method, thanks to the transient noise simulator in ELDO and to a period extractor (ELDO-FAS based language software) has been worked out, making it is possible to deduce the VCO phase noise.With this kind of simulation, it is possible to evaluate the effect of the various noise sources in the VCO on the period jitter. Two VCOs, with optimized phase noise, have been designed for Intermediate Frequency integrated circuits. The first VCO, using a LC (inductance - capacitance) resonant architecture(the inductance is located outside the integrated circuit) has been designed and implemented. The frequency variation is produced by a variable capacitance. One of the major defects of the variable capacitor (parasitic phase displacement of the capacitive current) has been originally compensated. This VCO phase noise has been measured, simulated in many ways, with a good correlation. The period jitter simulation methodology has been so validated. A second VCO, of relaxation kind, completely integrated (it does not need any external element), dedicated to replace the first one, has been designed. Its architecture is based on RC (resistance - capacitance) elements in differential mode. It is able to operate with a low power supply (5V). Its phase noise has been optimized thanks to the previous methodology.

This paper presents a high-speed, broadband phase -locked loop (PLL) for RF transceiver in 65nm CMOS process. Programmable structures are used to improve the lock speed of the PLL, the charge pump and loop filter can be adjusted by digital bit to reduce locked time of PLL. An integrated voltage-control oscillator (VCO) with 75% tuning range and a high-speed divider are used to accomplish all the frequencies. To achieve a wide tuning range while keep a low gain and a low phase noise, the VCO uses switched capacitor array. Finally, the PLL realizes 6-12 GHz wide frequency coverage. The phase noise performance at 6GHz is -113dBc/Hz@lMHz. The layout area is only 0.5265mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Working at 1. 2V supply voltage, the power consumption of the circuit is 11.3432 mW. The lock time of the PLL after using AFC is about 15. 258us.

Phase-locked loops (PLL) in radio-frequency (RF) and mixed analog-digital integrated circuits (ICs) experience substrate coupling due to the simultaneous circuit switching and power/ground (P/G) noise which translate to a timing jitter. In this paper. an analysis of the PLL timing jitter due to substrate noise resulting from P/G noise and large-signal switching is presented. A general comprehensive stochastic model of the substrate and P/G noise sources in very large-scale integration (VLSI) circuits is proposed. This is followed by calculation of the phase noise of the constituent voltage-controlled oscillator (VCO) in terms of the statistical properties of substrate and P/G noise. The PLL timing jitter is then predicted in response to the VCO phase noise. Our mathematical method is utilized to study the jitter-induced P/G noise in a CMOS PLL, which is designed and simulated in a 0.25-/spl mu/m standard CMOS process. A comparison between the results obtained by our mathematical model and those obtained by HSPICE simulation prove the accuracy of the predicted model.

The introduction of phase-locked loop (PLL) in a weak grid is not conducive to the stability of grid-inverter system. The small signal model of PLL is established in the form of complex variable, and the influence of PLL on the stability of inverter is analyzed. Starting with the disturbance components of voltage, current and duty cycle brought by PLL, the opposite amount is injected into the controller to reduce the negative influence of PLL, so as to suppress the frequency coupling and improve the stability of inverter. The experimental results demonstrate the effectiveness of the proposed strategy. Comparing the proposed control strategy with the method of reducing the bandwidth of the PLL and adding the virtual impedance method in the PLL structure, the experimental results show that the dynamic performance of the inverter is better after adopting the proposed strategy.

A 24-GHz fully integrated integer-N phase-locked loop (PLL) is presented in this paper. Benefiting from the bias noise filtering technique, the voltage controlled oscillator (VCO) in the loop achieves a low phase noise. Moreover, the supply voltage of VCO is as low as 0.8-V due to the low-threshold-voltage transistors used in the design. The proposed PLL is fabricated in 90-nm CMOS technology. The measurement results show that the PLL achieves a phase noise of -85dBc/Hz in band and -112dBc/Hz at 10-MHz offset from the carrier frequency of 24GHz. The whole chip occupies an area of 1.3 × 0.8mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 36-mW from a 1.2-V supply voltage (a 0.8-V supply voltage for VCO) excluding output driving buffers.

PurposeThe primary aim of this paper is to present a novel design approach for a ring voltage-controlled oscillator (VCO) suitable for L-band applications, whose oscillation frequency is less sensitive to power supply variations. In a few decades, with the advancement of modern wireless communication equipment, there has been an increasing demand for low-power and robust communication systems for longer battery life. A sudden drop in power significantly affects the performance of the VCO. Supply insensitive circuit design is the backbone of uninterrupted VCO performance. Because of their important roles in a variety of applications, VCOs and phase locked loops (PLLs) have been the subject of significant research for decades. For a few decades, the VCO has been one of the major components used to provide a local frequency signal to the PLL.Design/methodology/approachFirst, this paper chose to present recent developments on implemented techniques of ring VCO design for various applications. A complementary metal oxide semiconductor (CMOS)-based supply compensation technique is presented, which aims to reduce the change in oscillation frequency with the supply. The proposed circuit is designed and simulated on Cadence Virtuoso in 0.18 µm CMOS process under 1.8 V power supply. Active differential configuration with a cross-coupled NMOS structure is designed, which eliminates losses and negates supply noise. The proposed VCO is designed for excellent performance in many areas, including the L-band microwave frequency range, supply sensitivity, occupied area, power consumption and phase noise.FindingsThis work provides the complete design aspect of a novel ring VCO design for the L-band frequency range, low phase noise, low occupied area and low power applications. The maximum value of the supply sensitivity for the proposed ring VCO is 1.31, which is achieved by changing the VDD by ±0.5%. A tuning frequency range of 1.47–1.81 GHz is achieved, which falls within the L-band frequency range. This frequency range is achieved by varying the control voltage from 0.0 to 0.8 V, which shows that the proposed ring VCO is also suitable for low voltage regions. The total power consumed by the proposed ring VCO is 14.70 mW, a remarkably low value using this large transistor count. The achievable value of phase noise is −88.76 dBc/Hz @ 1 MHz offset frequency, which is a relatively small value. The performance of the proposed ring VCO is also evaluated by the figure of merit, achieving −163.13 dBc/Hz, which assures the specificity of the proposed design. The process and temperature variation simulations also validate the proposed design. The proposed oscillator occupied an extremely small area of only 0.00019 mm2 compared to contemporary designs.Originality/valueThe proposed CMOS-based supply compensation method is a unique design with the size and other parameters of the components used. All the data and results obtained show its originality in comparison with other designs. The obtained results are preserved to the fullest extent.

A 1.8-2 GHz fully integrated CMOS phase-locked-loop (PLL) frequency synthesizer for CDMA receivers is presented. The design focuses on the voltage controlled oscillator (VCO) and loop bandwidth adaptation technique, which determine the out-of-band phase noise and the speed of the PLL frequency synthesizer, respectively. A low power low phase noise bond wire VCO is proposed. The inductance compensation control circuit combined with the switched-capacitor array is used to automatically compensate the bond wire inductance variation. A novel lock detector that adoptively controls the loop bandwidth is employed. Implemented in a 0.18 /spl mu/m CMOS technology and at a 1.8 V supply voltage, the PLL frequency synthesizer dissipates 24 mW and occupies a chip area of 2.6 mm/spl times/1.6 mm. The simulation results show that phase noise of the synthesizer is -122.6 dBc/Hz at 1 MHz offset frequency and the settling time is 70 /spl mu/s.