A Fully Digital Delay Line Based GHz Range Multimode Transmitter Front-End in 65-nm CMOS

A fully digital burst-mode handheld transmitter with power amplifier for the 900-MHz band is presented. The transmitter front-end consists of a digital polar modulator which uses pulse width modulation (PWM) for the amplitude modulator. Phase modulation (PM) is implemented by shifting the carrier in time. Both the PWM and the PM are implemented using asynchronous delay lines which allow time resolutions down to 10 ps without the need for high-frequency clock signals. The modulated signal is amplified by a Class B amplifier which uses power combining to reach watt-level output power. The transmitter is implemented in standard CMOS technology. When transmitting a modulated signal with a peak-to-average power ratio (PAPR) of 10.3 dB and 5-MHz bandwidth, the burst-mode transmitter meets the stringent error-vector-magnitude (EVM) specifications of 5.6% at 23.1-dBm average output power with 11.7% power added efficiency (PAE).

To create efficient telecommunication systems we need efficient telecommunication devices. The most energy-consuming element of any radio transmitting equipment is the radio frequency (RF) power amplifier (PA). The highest efficiency of a RF PA can be achieved when its elements operate in switching modes namely in classes D, E, F. Modern efficient telecommunication signals use simultaneous amplitude and phase modulation. Switching PA cannot directly amplify variable amplitude signals. To solve the problem various “synthetic” methods of linear amplification are used. The most promising of these are Kahn method (EER-Envelope Elimination and Restoration). To increase the transmission speed it is necessary to expand the bandwidth of the used frequencies, which is limited by the pulse width modulation (PWM) amplifier of the EER PA envelope path. Multiphase PWM is one way to solve this problem. The use of multiphase PWM in the EER PA envelope path can effectively reduce unwanted PWM conversion products. This will increase the effective bandwidth of amplified frequencies. The article defined efficiency of unwanted components suppression in multiphase PWM, depending on the number of LPF elements for a different number of phases. The requirements for acceptable channel asymmetry in multiphase PWM have been determined. They are quite high and should be taken into account when designing practical devices.

This article presents an analog linearizer that linearizes multiple power amplifiers (PAs) by configuring target predistortion curves, including tunable slopes for both amplitude modulation (AM)–AM and AM-phase modulation (PM) curves, as well as adjustable critical output power points for each curve. Moreover, general memoryless nonlinear models for analog linearizers are proposed, and a boundary parameter-searching approach based on the error vector magnitude (EVM) gradient optimization is introduced to determine the optimal maximum expansion of gain and phase. Prototype validation involves linearization of both a GaN PA and a CMOS PA. The proposed linearizer is implemented in a 65-nm CMOS process, employing nonlinear inductive techniques and diode-connected methods for continuous adjustments in phase and gain expansion. Matching strategies are discussed to increase the corresponding expansion range while decoupling AM-AM and AM-PM. Gain adjustments are determined to control the critical output power points. The experiment shows that the designed linearizer achieves a gain expansion of over 3.5 dB and a phase expansion exceeding 25° at 35 GHz while consuming approximately 74.2 mW. Modulated signal measurements in four scenarios demonstrate significant EVM improvements. Specifically, for the GaN PA with a signal of 256-quadrature amplitude modulation (QAM) and a 400-MHz bandwidth, EVM can be reduced from 6.6% to 2.9% at 31.3 dBm. For the CMOS PA under the same conditions, EVM can be improved from 6% to 2.8%. Overall, this article provides a universal solution for low-cost linearization of various PAs.

This paper presents a CMOS inverter-like Class-D/E switching power amplifier (PA). The proposed amplifier operates in-between Class-E and Class-DE PAs. For proper operation of a Class-E PA, an RF choke (RFC) with large inductance value and high self-resonant frequency is necessary. A Class-DE PA does not require an RFC but requires a dead-time between OFF-ON transitions of the two switches. The proposed PA uses two complementary switches and requires neither an RFC nor a dead-time for its operation. For the same supply voltage and the load resistance, the voltage stress on each switching device in the proposed PA is less than the voltage stress in a Class-E PA. Design and simulation results of a prototype PA at 2.45 GHz with +20 dBm output power are presented.

For the amplitude modulation (AM) radio broadcast band, there are several standards being considered for digital audio broadcast (DAB), all using orthogonal frequency-division multiplexing (OFDM). One of the main challenges to implementing digital audio broadcasting is that existing broadcast equipment was not designed for it. Unlike analog AM, which is a low bandwidth amplitude modulated signal, OFDM is a noise-like signal with significant amplitude and phase modulation. Most AM transmitters use an envelope elimination and restoration (EER) amplifier architecture, where the amplitude and phase components of the signal are amplified separately then recombined at the high power stage. The magnitude and phase component bandwidths are several times that of the input signal, and any filtering in the amplifier will result in spectral regrowth due to poor cancellation of this high frequency content. This paper develops the concept of using time-domain preprocessing on the signal to reduce the bandwidth expansion in EER amplifiers. The processing exploits the localization of the bandwidth expansion and its correlation with spectral regrowth at the output. The proposed algorithm identifies distortion- causing signal sections and replaces each one with an alternative signal trajectory. Using the processing, out of band emissions are reduced at the expense of increased computational complexity and error vector magnitude. Promising results are shown for the DRM 10 kHz digital signal, with reductions in spectral regrowth of up to 10 dB.

The drives of power amplifiers of magnetic levitation servo spindle applied to micro EDM (Electron discharge machining) based on FPGA (Field programmable gate array) are developed. The drive module that produces the PWM (Pulse width modulation) waves that conform to the requirements of spindle power amplifiers involving three-level half bridge switch power amplifier, three-level full bridge switch power amplifier and motor power amplifier, according to input of action values from magnetic levitation servo spindle controller DSP (Digital signal processor) is designed. Multi-PWM producing algorithm by single timer with multi comparing nodes is proposed. After being applied to control system of magnetic levitation servo spindle, the drives accomplish conversion from DSP action values to PWM waves. The PWMs that drive radial coil current power amplifier have phase difference of 180°. The PWMs that drive axial coil current power amplifier have dead zone time and their wave shapes are complementary. The PWMs that drive the motor power amplifier conform to requirements of power amplifier chip LMD18200. Using FPGA to realize the drive function of spindle power amplifier makes the drive design more flexible, resource distribution of DSP more optimized, the task of algorithms running more centralized, and the drives module gets simpler and more reliable because the phase shift circuit and dead zone circuit are cancelled but the function of phase shift and dead zone is reserved.

A cascode configuration in class-E CMOS power amplifiers (PAs) provides high reliability with respect to breakdown considerations. However, it causes a power loss due to the slow transition of a common-gate device from the triode region to the cut-off region. To minimize the power loss of cascode class-E CMOS PAs, we propose a charging acceleration technique, CAT. This method incorporates a capacitive element between the drain and the source of a common-gate device in a cascode configuration, accelerating the charging speed responsible for turning off a common-gate device instantly after a common-source device is turned off and thus minimizing power loss from the device. We compared the performance of the proposed cascode class-E PA to that of the conventional cascode class-E PA using a 0.18- CMOS process. With a 3.3-V power supply, the proposed fully-integrated CMOS PA achieves 30.7 dBm of maximum output power and 45.6% of power-added efficiency (PAE) with a dynamic range of 40 dB at 1.6 GHz. According to measurements, the proposed cascode class-E PA shows improvement in PAE over the conventional class-E PA of between 5% and 9% in a 1.5 to 2.0 GHz range.

The analysis and implementation of a dual-band direct-conversion millimeter-wave transmitter is presented. The proposed dual-band modulator uses high-impedance loads at two frequencies for the local oscillator driving amplifiers and power amplifier (PA) pre-amplifiers. To correct the amplitude and phase imbalance of the in-phase and quadrature channels at Q- and W-bands, the paper suggests a digitally controlled quadrature error correction stage to finely calibrate these errors and lower the error vector magnitude (EVM) without increasing the baseband digital-to-analog converter resolution. The transmitter is fabricated in 0.12- μm silicon-germanium BiCMOS process and occupies an area of 5.5 mm 2 . At 45-GHz carrier frequency, error correction improves the sideband suppression ratio (SSR) by 10 dB at 2.4-MHz IF frequency. The EVM is lowered from 3.21% to 2.38% for a 64-QAM constellation at a 2.4-Ms/s symbol rate. At 94-GHz carrier frequency, the SSR is improved from 24 to 41 dBc at 2.4-MHz IF frequency, and the EVM is lowered by more than 1% for a 16-QAM constellation at 3-Ms/s symbol rate. A dual-band PA breakout measurement indicates the peak power-added efficiency of 15% with 14-dBm maximum saturated power (Psat) at 43 GHz and 9-dBm Psat at 82 GHz is achieved.

An inductive link, driven by a Class-E power amplifier (PA), is the most widely used method to transfer power to medical implants. Frequency-shift keying (FSK) is a robust data modulation scheme with negligible sensitivity to amplitude noise and movements of the transmitter and receiver coils of an inductive link. However, implementing FSK modulation on a Class-E PA has been a daunting task as high-Q Class-E PAs used for remote powering are narrowband circuits, while high data rate FSK modulation demands a wideband amplifier. In this paper, we propose a Class-E PA which uses wideband FSK modulation to transfer power and data to a medical implant. In the proposed circuit, the PA is effectively switched between two load networks that keep the amplifier tuned at both carrier frequencies used for data modulation. Using this approach and with carrier frequencies of 2 and 4 MHz, we have implemented a wireless power and data transfer link which can transmit data at a rate of 1 Mbps and with a bit error rate of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> . The power transfer efficiency and the power delivered to the load, with a 7.1-μH transmitter coil and a 1.2-μH receiver coil, separated by a 6-mm air gap, were measured to be 25% and 126 mW, respectively.

Current radio communication systems that adopt amplitude and phase modulations demand high linearity and high efficiency. The cascade connection between digital baseband pre-distorter (DPD) and power amplifier (PA) can be a cost-effective solution to guarantee the required linearity without compromising the efficiency. In the design of a DPD for a single band PA, direct learning can be used to extract the pre-inverse parameters or, alternatively, indirect learning can be employed by exchanging the position of the system during the identification procedure to avoid the necessity of a PA model within a closed-loop process. The performance of direct learning is substantially dependent on the accuracy of the behavioral model that replaces the PA. Furthermore, in a practical environment where only an approximation to the inverse is achieved, the linearization capability of the indirect learning is affected by shifting the post-inverse placed after the PA to a pre-inverse located before the PA. For concurrent dual-band PAs, an additional advantage of the indirect approach is that the post-inverse identifications for each band are completely independent of each other. In an authors’ previous work, a comparative analysis between the two learning architectures applied to the linearization of concurrent dual-band PAs was performed based on DPDs modeled by polynomials with memory. This work contributions are the extension of such comparative analysis to DPDs modeled by artificial neural networks, the development of complex-valued three-layer perceptrons suitable for concurrent-dual band DPDs and the introduction of a modified indirect approach to improve the accuracy of previous direct and indirect learnings. Spectre-RF transient simulations are performed in the circuit-under-test described by a wideband 130 nm CMOS PA concurrently stimulated by 2.4 GHz Wi-Fi and 3.5 GHz LTE signals. Reported simulation results show that, in a comparison with the previous direct and indirect learnings with similar output mean powers of about 60 mW, the modified indirect approach provides a superior linearity performance. The modified indirect learning reduces the error vector magnitude (EVM) metric to 0.87% and 1.13% for Wi-Fi and LTE bands, respectively, whereas the indirect and direct learnings achieve EVM equal to or larger than 1.05% and 1.49% for Wi-Fi and LTE bands, respectively.

Digital predistortion (DPD) has been widely used to linearize the power amplifiers (PAs) by capturing the PA nonlinear distortion and pre-distorting the PA input. However, both the capturing and the signal processing procedures are time consuming and not applicable to fast frequency-hopping systems. This paper explores the feasibility of constructing a wideband signal to extract DPD coefficients for frequency-hopping systems. The frequency range of the wideband signal is designed to cover all hopping frequencies, as such the nonlinear characteristics of the PA at all hopping frequencies are included during the estimation of the DPD coefficients. Thus, only one set of coefficients is needed to linearize the PA over a wide frequency range. Experiment is performed on a self-designed testbed, which demonstrates that the proposed method can be used to effectively linearize the narrowband signals over different carrier frequencies.

The burst-mode transmitter has been proposed as an efficiency enhancement technique for signals with high peak-to-average-power ratios (PAPRs), where appropriate modulation schemes such as pulse-width modulation (PWM) are used to generate a switching signal to drive the radio frequency (RF) power amplifier (PA). Ideally, a PWM signal is of infinite bandwidth, however, high-frequency spectral components are attenuated, e.g., by the bandlimitation of the PA matching network or the PWM circuit itself. Bandlimitation introduces ripples in the signal amplitude, which might reduce the PA efficiency in burst-mode operation. In this paper, we show that a bandlimited PWM signal does not necessarily degrade the overall transmitter efficiency because of the higher coding efficiency. The coding efficiency of bandlimited PWM signals, i.e., PWM signals with a finite number of harmonics, is derived analytically and verified by measurements. Additionally, from the measurements, we exemplarily determine the number of harmonics for bandlimited PWM signals with the best transmitter efficiency-linearity trade-off, and therefore demonstrate the excellence of bandlimited PWM for burst-mode transmitters in terms of transmitter efficiency as well as transmission signal quality.

In this paper we report the results of extensive research on phase modulation (PM) and amplitude modulation (AM) noise in linear bipolar junction transistor (BJT) amplifiers. BJT amplifiers exhibit 1/f PM and AM noise about a carrier signal that is much larger than the amplifier's thermal noise at those frequencies in the absence of the carrier signal. Our work shows that the 1/f PM noise of a BJT based amplifier is accompanied by 1/f AM noise which can be higher, lower, or nearly equal depending on the circuit implementation. The 1/f AM and PM noise in BJTs is primarily the result of 1/f fluctuations in transistor current, transistor capacitance, circuit supply voltages, circuit impedances, and circuit configuration. We discuss the theory and present experimental data in reference to common emitter amplifiers, but the analysis can be applied to other configurations as well. This study provides the functional dependence of 1/f AM and PM noise on transistor parameters, circuit parameters, and signal frequency, thereby laying the groundwork for a comprehensive theory of 1/f AM and PM noise in BJT amplifiers. We show that in many cases the 1/f PM and AM noise can be reduced below the thermal noise of the amplifier.

In this paper, a selective harmonic mitigation pulse width and amplitude modulation (SHM-PWAM) control strategy, for three-phase four-leg inverters has been proposed. In this way, the pulse amplitude modulation (PAM), which is mainly used in communication systems, is applied simultaneously with the pulse width modulation (PWM), to the three-phase four-leg inverter. Considering PAM increases the system degrees of freedom in mitigating harmonics compared with the conventional PWM strategy. The control signals of three legs voltage source inverter, mathematically expressed using Fourier-based equations to eliminate lower order nontriplen harmonics, and the fourth leg produces the harmonics that are equal to the lower order triplen harmonics which produced by the other legs. Simulation results show the performance of the SHM-PWAM strategy from the THD point of view, compared with SHM-PWM strategy.

Acoustic holography underpins the number of modern acoustics applications. The usage of multi-focal acoustic holograms with phased array transducers (PATs) in ultrasonic tactile displays and acoustic levitation are increasing, and achieving a high-quality hologram are of significant interest. Inspired by the latest optical hologram optimizer, we developed a novel acoustic hologram optimizer for PATs called Diff-PAT [T. Fushimi, K. Yamamoto, and Y. Ochiai, “Acoustic hologram optimisation using automatic differentiation”]. Diff-PAT is based on a gradient-descent algorithm and automatic differentiation. The performance of Diff-PAT was numerically evaluated using three array configurations and it achieved superior accuracy over the conventional optimizers. For example, when two focal points are generated with 196 ultrasonic (40 kHz) transducers; the state of art optimizer (with phase and amplitude modulation) based on Eigensolver has an average error of 4.07 % where Diff-PAT (with only phase modulation) achieve average error of 0.0174%. These results show that amplitude and phase modulation may not be necessary for PATs to be successful. Furthermore, we demonstrate the versatility of Diff-PAT by applying it to binary acoustic holograms, simultaneous modulation of acoustic amplitude and phase at the target plane, and phase plates. [Work supported by Pixie Dust Technologies, Inc., Diff-PAT is patent pending (JP2020-167367A).]