A Gate Driver with Integrated Dead-Time Controller

Under-resonant operation of an ideal multi-resonant series-parallel power converter (MRSPC) with a capacitive output filter is modeled in this paper. This operation allows zero current switching (ZCS), which is convenient for bipolar devices. The capacitive output filtering reduces the recovery effect of the rectifier diodes and is suitable for high output voltage applications. A closed-form solution is found for this power converter, based on state space analysis using energy concepts. This approach simplifies the mathematical operations and gives better physical insight of the system variables. Based on the model, the steady-state characteristics of this power converter are derived by a simulation program, which are discussed and compared with the series resonant half-bridge power converter (SRHC). The optimum power converter parameters are found for given design requirements using computerized optimization routines. Several design examples are presented and compared with SRHC. The validity of the model is verified by SPICE simulations.

Discontinuous operation of a half-bridge PWM power converter with a current-doubler rectifier is analyzed in this paper. The converter is found to exhibit six different discontinuous conduction modes depending on the control methods (symmetrical or asymmetrical control) as well as whether discrete or integrated magnetics are used. The definition of each mode, boundary conditions among the different modes, and steady-state characteristics of the converter under each mode are presented. Simulation and experimental results are provided for verification of the analysis results.

In present scenario, reliable operation of power converters must be ensured to enable continuous operation of large rated generating units. With respect to this aim, this paper adopts shared-leg fault tolerant operation for a 5-channel three level neutral point clamped back-to-back power converters (3L- NPC) serving to a typical 250 MW doubly-fed induction machine (DFIM) unit. Under open switch fault condition, faulty leg is identified and isolated with the help of normalized phase current average fault diagnosis method. Thereafter, grid side converter (GSC) and rotor side converter (RSC) share a common leg to deliver the required power to the rotor circuit of DFIM. For this effective operation, double zero-sequence signal is computed and injected into vector control strategy for independent control of GSC and RSC. Furthermore, shared-leg current capability, converter output voltage capability, dc-link voltage oscillations and its thermal performance are analyzed during fault tolerant operation. From the observed test results, two operating conditions are proposed: (i) reduced real power delivery by adjusting speed of hydraulic turbine and (ii) rated real power delivery by absorbing reactive power from the grid. To examine and demonstrate the proposed methodology MATLAB/Simulink2014A tool is used for a 250 MW DFIM unit. An experimental demonstration is performed with 2.2 kW DFIM unit.

The trend in the development of power converters is focused on efficient systems with high power density, reliability and low cost. The challenges to cover the new power converters requirements are mainly concentered on the use of new switching-device technologies such as silicon carbide MOSFETs (SiC). SiC MOSFETs have better characteristics than their silicon counterparts; they have low conduction resistance, can work at higher switching speeds and can operate at higher temperature and voltage levels. Despite the advantages of SiC transistors, operating at high switching frequencies, with these devices, reveal new challenges. The fast switching speeds of SiC MOSFETs can cause over-voltages and over-currents that lead to electromagnetic interference (EMI) problems. For this reason, gate drivers (GD) development is a fundamental stage in SiC MOSFETs circuitry design. The reduction of the problems at high switching frequencies, thus increasing their performance, will allow to take advantage of these devices and achieve more efficient and high power density systems. This Thesis consists of a study, design and development of active gate drivers (AGDs) aimed to improve the switching performance of SiC MOSFETs applied to high-frequency power converters. Every developed stage regarding the GDs is validated through tests and experimental studies. In addition, the developed GDs are applied to converters for wireless charging systems of electric vehicle batteries. The results show the effectiveness of the proposed GDs and their viability in power converters based on SiC MOSFET devices. La tendencia en el diseño y desarrollo de convertidores de potencia está enfocada en realizar sistemas eficientes con alta densidad de potencia, fiabilidad y bajo costo. Los retos para cubrir esta tendencia están centrados principalmente en el uso de nuevas tecnologías de dispositivos de conmutación tales como, MOSFETs de carburo de silicio (SiC). Los MOSFETs de SiC presentan mejores características que sus homólogos de silicio; tienen baja resistencia de conducción, pueden trabajar a mayores velocidades de conmutación y pueden operar a mayores niveles de temperatura y tensión. A pesar de las ventajas de los transistores de SiC, existen problemas que se manifiestan cuando estos dispositivos operan a altas frecuencias de conmutación. Las rápidas velocidades de conmutación de los MOSFETs de SiC pueden provocar sobre-voltajes y sobre-corrientes que conllevan a problemas de interferencia electromagnética (EMI). Por tal motivo, el desarrollo de controladores de puertas es una etapa fundamental en los MOSFETs de SiC para eliminar los problemas a altas frecuencias de conmutación y aumentar su rendimiento. En consecuencia, aprovechar las ventajas de estos dispositivos y lograr sistemas más eficientes y con alta densidad de potencia. En esta tesis, se realiza un estudio, diseño y desarrollo de controladores activos de puerta para mejorar el rendimiento de conmutación de los MOSFETs de SiC aplicados a convertidores de potencia de alta frecuencia. Los controladores son validados a través de pruebas y estudios experimentales. Además, los controladores de puerta desarrollados son aplicados en convertidores para sistemas de carga inalámbrica de baterías de vehículos eléctricos. Los resultados muestran la importancia de los controladores de compuerta propuestos y su viabilidad en convertidores de potencia basados en carburo de silicio.

This paper proposes a zero-voltage transition (ZVT) PWM synchronous buck converter, which is designed to operate at low output voltage and high efficiency typically required for portable systems. To make the DC-DC converter efficient at lower voltage, synchronous converter is an obvious choice because of lower conduction loss in the diode. The high-side MOSFET is dominated by the switching losses and it is eliminated by the soft switching technique. Additionally, the resonant auxiliary circuit designed is also devoid of the switching losses. The suggested procedure ensures an efficient converter. Theoretical analysis, computer simulation, and experimental results are presented to explain the proposed schemes.

This paper presents a scheme for synchronous buck converter aiming at ripple cancellation to obtain zero output current ripple in the power converter and improve its load transient response. The paper analyses a controlled coupled inductor-based LL-LC filter network in a synchronous buck converter designed for high power and high frequency applications. The design provides significant ripple cancellation in output current of the converter with significantly improved transient response by means of an auxiliary circuit. This was verified in MATLAB® for both open as well as closed loop converter systems. The effectiveness of the design has been validated by demonstrating zero-ripple output current in a 48 V to 12 V, 100 kHz, 60 W synchronous buck converter.

Chapter 14 - Power converter solutions and controls for green energy

This article describes a novel resonant gate driver for charging the gate capacitor of power metal-oxide semiconductor field-effect-transistors (MOSFETs) that operate at a high switching frequency in power converters. The proposed resonant gate driver is designed with three small MOSFETs to build up the inductor current in addition to an inductor for temporary energy storage. The proposed resonant gate driver recovers the CV2 gate loss, which is the largest loss dissipated in the gate resistance in conventional gate drivers. In addition, the switching loss is reduced at the instants of turn on and turn off in the power MOSFETs of power converters by using the proposed gate driver. Mathematical analyses of the total loss appearing in the gate driver circuit and the switching loss reduction in the power switch of power converters are discussed. Finally, the proposed resonant gate driver is verified with experimental results at a switching frequency of 1 MHz.

The effect of varying the driving strength of the gate driver IC on the efficiency of synchronous buck converters is the focus of this work. To reduce the switching losses in the output stage, gate drivers are often designed to charge and discharge the gate electrodes of the power MOSFETs as fast as possible. However, fast switching requires power hungry gate drivers and the gate driver power consumption could exceed the switching loss at light load. In this work, a segmented gate driver IC with adjustable driving capability is presented. By choosing the appropriate gate driving capability for each particular load condition, it is possible to continuously optimize the overall power conversion efficiency. In a 20W DC-DC converter, regulated at 1.2V, 0-20A output, a 7% efficiency improvements at light load and significant reduction in ringing and overshoot at the switching node is achieved with the proposed 0.25μm CMOS compatible gate driver IC.

Power converters based on Wide Bandgap Devices (WBD) are able to operate at high-frequency and high-voltage. In such synchronous converters a very short dead-time is advised because a lot of WBD do no have a parasitic body diode to conduct current in reverse. Into a high-voltage inverter, isolators generate isolated floating gate signals from logic level input signals. Mismatch between high-side and low-side signal propagation delays involves setting a long secure dead-time. To overcome this matching issue in order to guarantee the dead-time duration and time location, we propose other input signal propagation paths. Both input signals pass through a single low-side 2-channel digital isolator and one isolated signal is translated to the high-side gate driver by a high-speed monolithically integrated level-shifter. The proposed voltage level translator structure has been implemented with a high-voltage diode-less SiC vertical JFET and low voltage MOSFETs. At 240V power supply voltage and 100 kHz switching frequency, the level-shifter propagation delay is only 10 ns with a 1.85 mA supply current. Moreover an effective built-in current regulator prevents the circuit from any current spikes, overvoltage and overconsumption. Such topology allows to safely set a very short 23 ns dead-time and improves WBD-based converter operations while reducing size and price.

An improved half-bridge type ZVS-PWM DC-DC power converter which uses a saturable reactor-assisted soft-switching technique is presented in this paper. The power converter with a high-frequency transformer link has many advantages such as lower switching and conduction losses, load operation in wide range, constant frequency operation and minimized EMI. Its operating principle is illustrated and its steady-state circuit analysis is carried out. In order to demonstrate the remarkable effectiveness of the converter characteristics, feasible experiments are carried out with a 150 W-200 kHz prototype.

An improved half-bridge type ZVS-PWM DC-DC power converter which uses a saturable reactor-assisted soft-switching technique is presented in this paper. The power converter with a high-frequency forward and flyback hybrid transformer link has many advantages such as lower switching and conduction losses, load operation in a wide range, constant frequency operation and minimized EMI. Its operating principle is illustrated and its steady-state circuit analysis are carried out. In order to demonstrate the remarkable effectiveness of the converter characteristics, feasible experiments are actually carried out with a 150 W-200 kHz prototype converter using power MOSFETs.

In order to study the effects of large HVDC power converters on the feeding AC networks, it is of importance to explain and to calculate harmonic phenomena which are a result of power converter operation. During commissioning of real HVDC power converters, it could be seen that harmonics resulting from asymmetry in the system voltages or from asymmetry in power converter operation led to significant difficulties concerning the system design. For this reason, not only the effects of characteristics but also the effects of noncharacteristic converter harmonics must be taken into account. The aim is to describe the steady state harmonic behavior of the converter. The harmonic spectra are not determined by time domain analysis but instead the solution is found by frequency domain calculations. This can result in reduced calculation time in comparison to conventional Fourier analysis of the time functions. The power converter is interpreted as an amplitude modulator with voltage and current converter functions which describe the coupling of the DC circuit and the AC network through the power converter. To verify the theory, comparisons of frequency domain with time domain calculations were carried out. >

Normally‐ON silicon carbide junction‐field‐effect transistors have a simple design and exhibit advantageous performance in terms of losses, elevated junction temperatures and high switching frequencies. However, under a loss of power to their gate, normally‐ON junction‐field‐effect transistors are subject to a shoot‐through situation, which might be severe for their survivability. This paper presents a universal concept for an automatic and self‐powered gate driver power supply circuit for normally‐ON silicon carbide junction‐field‐effect transistors employed in high input‐impedance circuits. The power to the gate is supplied during start‐up and steady‐state operations through a mutually coupled inductor with the high input impedance inductor and by employing a typical low‐voltage, power supply circuit. The performance of the proposed automatic and self‐powered gate driver was evaluated on a DC/DC boost converter rated at 6 kW, as well as in a low‐voltage solid‐state DC circuit breaker. From experiments it is shown that using the proposed circuit, the start‐up process requires approximately 350 s, while the steady‐state switching process of the junction‐field‐effect transistor during steady‐state is also shown. Using the proposed circuit in a low‐voltage solid‐state DC breaker, a fault current of 68 A is cleared within 155 s.

This work explores the principle of utilizing gallium nitride devices as a gate driver for silicon carbide power devices. As silicon has long reached its performance limits, Wide Bandgap semiconductors such as gallium nitride and silicon carbide have emerged as promising alternatives due to their superior characteristics. However, few publications suggest using a gallium nitride-based gate driver for silicon carbide, high-voltage power devices. Unlike standard voltage source gate drivers, this paper proposes a novel bi-polar current source resonant gate driver topology using gallium nitride transistors as a gate drive circuit for silicon carbide power switching. The driver receives a single input supply and pulsed width modulation signal, producing a high current bi-polar gate driving signal. The gate driver is validated by employing the proposed gate driver to a high-power silicon carbide transistor in a resonant boost converter. The experimental results show that the new gate driver recovers the gate charge wasted energy and provides high performances in varying high voltage loads at a 2.5 MHz switching frequency while reducing the gate losses by 26%.