A Hardware-Oriented IME Algorithm for HEVC and Its Hardware Implementation

The growing popularity of high resolution video and the continuously increasing demands for high quality video on mobile devices are producing stronger needs for more efficient video encoder. Concerning these desires, HEVC, a newest video coding standard, has been developed by a joint team formed by ISO/IEO MPEG and ITU/T VCEG. Its design goal is to achieve a 50% compression gain over its predecessor H.264 with an equal or even higher perceptual video quality. Motion Estimation (ME) being as one of the most critical module in video coding contributes almost 50%-70% of computational complexity in the video encoder. This high consumption of the computational resources puts a limit on the performance of encoders, especially for full HD or ultra HD videos, in terms of coding speed, bit-rate and video quality. Thus the major part of this work concentrates on the computational complexity reduction and improvement of timing performance of motion estimation algorithms for HEVC standard. First, a new strategy to calculate the SAD (Sum of Absolute Difference) for motion estimation is designed based on the statistics on property of pixel data of video sequences. This statistics demonstrates the size relationship between the sum of two sets of pixels has a determined connection with the distribution of the size relationship between individual pixels from the two sets. Taking the advantage of this observation, only a small proportion of pixels is necessary to be involved in the SAD calculation. Simulations show that the amount of computations required in the full search algorithm is reduced by about 58% on average and up to 70% in the best case. Secondly, from the scope of parallelization an enhanced TZ search for HEVC is proposed using novel schemes of multiple MVPs (motion vector predictor) and shared MVP. Specifically, resorting to multiple MVPs the initial search process is performed in parallel at multiple search centers, and the ME processing engine for PUs within one CU are parallelized based on the MVP sharing scheme on CU (coding unit) level. Moreover, the SAD module for ME engine is also parallelly implemented for PU size of 32×32. Experiments indicate it achieves an appreciable improvement on the throughput and coding efficiency of the HEVC video encoder. In addition, the other part of this thesis is contributed to the VLSI architecture design for finding the first W maximum/minimum values targeting towards high speed and low hardware cost. The architecture based on the novel bit-wise AND scheme has only half of the area of the best reference solution and its critical path delay is comparable with other implementations. While the FPCG (full parallel comparison grid) architecture, which utilizes the optimized comparator-based structure, achieves 3.6 times faster on average on the speed and even 5.2 times faster at best comparing with the reference architectures. Finally the architecture using the partial sorting strategy reaches a good balance on the timing performance and area, which has a slightly lower or comparable speed with FPCG architecture and a acceptable hardware cost

本文提出了一种HEVC视频编码的运动估计快速算法，该算法可以显著加速搜索过程，编码效率与HEVC参考软件(Test Model)中的Test Zone Search (TZSearch)平分秋色。较之H.264/AVC视频标准，HEVC引入了更为复杂的混合编码框架和更大尺寸的搜索窗口，从而带来了更高的计算复杂度。为了降低复杂度，我们提出了一种新的运动估计算法，该算法仅利用搜索窗中所选取的少量几个点建立二次曲面模型，通过对像素的绝对差值和(SAD)分布的迭代分析，逐步缩小搜索范围，直到得出最优的运动矢量。该算法可被用于不同的编码环境中，实验结果表明，与HM相比，该算法可以节约大约40%的运动估计算法时间，仅引起轻微的性能损失。 This paper presents a motion estimation (ME) algorithm for High Efficiency Video Coding (HEVC), which provides a strategy to speed up the search process significantly, while yielding the same quality performance as the Test Zone Search (TZSearch) scheme in HEVC Test Model (HM). Compared with the H.264/AVC, HEVC employs a more complex hybrid coding architecture and a larger size search window, leading to great computational complexity. In order to reduce the complexity, a novel motion estimation algorithm is proposed, in which some limited pixels of certain position in the current search window are utilized to build a quadratic model, and then shrink the search range repeatedly by analyzing the sum of absolute difference (SAD) distribution until the best motion vector (MV) is obtained. The proposed algorithm can be applied to various encoding conditions. Experimental results show that our method can save 40% of computations compared with the HM, with negligible decrease of coding quality.

The emerging standard of High Efficiency Video Coding (HEVC) provides a 50% improved compression performance compared to its predecessor H.264/AVC at the expense of increasing its computational complexity which is due to a large number of modes involved in the decision process where it would increase encoding time and provide hardware limitations. In this paper, the reduction of intra-coding complexity is proposed by utilization of Rate-Distortion Optimization (RDO) in preselecting a mode with the best RD cost, among all 35 intra-modes. Two cost functions – Sum of Absolute Difference (SAD) and Sum of Absolute Transform Difference (SATD, available in the HEVC Test Model (HM) Reference Software, are determined by making encoder decisions. This paper compares the performance and complexity cost of SAD only for intra-mode, with SATD-based intra-mode by modifying the HM reference encoder through forced selection of the mentioned modes. Results show that SAD consistently produces the least encoding time among all modes, along with sensible values of bitrate. Furthermore, error concealment was introduced in decoding the video sequences with the use of IEEE 802.22 Standard which only allowed power gains resulting to packet error rates (PER) ranging from 1% to 30% for the analysis on the behavior of each video sequence in an environment where error is introduced.

Although advanced motion vector prediction (AMVP) modes based on motion estimation (ME) are selected significantly less due to the merge mode newly adopted in the high-efficiency video coding (HEVC), integer ME (IME) still occupies a large amount of computation in HEVC because the HEVC supports a highly flexible block partitioning structure. Introduction of the merge mode in HEVC substantially affects the optimal search algorithm of IME. Therefore, this gives a chance to reduce the computational complexity of ME with marginal drop of the compression efficiency. This paper proposes a new IME algorithm that significantly reduces its search ranges. Computational complexity of the proposed algorithm is reduced without serious degradation in coding efficiency by obtaining additional accurate motion vector predictors (MVPs) in a bottom-up order and searching narrow regions around multiple MVPs. These bottom-up MVPs are obtained from the prediction units (PUs) in the coding units (CUs) in the hierarchically lower level, which share the pixel area either completely or partially with the current PU. Although the encoder should perform the proposed IME in a bottom-up order from the smallest CUs to the larger CUs, several other processes, such as fractional ME and merges mode are performed in a top-down order to exploit several fast algorithms already adopted in the HEVC test model encoder. To keep compatibility with HEVC standard, the bottom-up MVPs are utilized for only IME. The bitstream is generated using standard AMVP. According to the simulation results, it is confirmed that the proposed algorithm improves the accuracy of MVPs, which leads to the reduction of IME computational complexity up to 81.95% on average with the Bjontegaard delta bitrate of 0.39%.

High quality videos became an essential requirement in recent applications. High efficiency video coding (HEVC) standard provides an efficient solution for high quality videos at lower bit rates. On the other hand, HEVC comes with much higher computational cost. In particular, motion estimation (ME) in HEVC, consumes the largest amount of computations. Therefore, fast ME algorithms and hardware accelerators are proposed in order to speed‐up integer ME in HEVC. This study presents a fast centre search algorithm (FCSA) and an adaptive search window algorithm (ASWA) for integer pixel ME in HEVC. In addition, centre adaptive search algorithm, a combination of the two proposed algorithms FCSA and ASWA, is proposed in order to achieve the best performance. Experimental results show notable speed‐up in terms of encoding time and bit rate saving with tolerable peak signal‐to‐noise ratio (PSNR) quality degradation. The proposed fast search algorithms reduce the computational complexity of the HEVC encoder by 57%. This improvement is accompanied with a modest average PSNR loss of 0.014 dB and an increase by 0.6385% in terms of bit rate when compared with related works.

The recent video compression standard, HEVC (high efficiency video coding), will most likely be used in various applications in the near future. However, the encoding process is far too slow for real-time applications. At the same time, computing capabilities of GPUs (graphics processing units) have become more powerful in these days. In this paper, we have proposed a GPU-based parallel motion estimation (ME) algorithm to enhance the performance of an HEVC encoder. A frame is partitioned into two subframes for pipelined execution to improve GPU utilization. The flow chart is redetermined to solve data hazards in the pipelined execution. Two new methods are introduced in the proposed ME: decision of a representative search center position (RSCP) and warp-based concurrent parallel reduction (WCPR). A RSCP employs motion vectors of a co-located CTU in a previously encoded frame to solve a dependency problem in parallel computation with negligible coding loss. WCPR concurrently executes several parallel reduction operations, which increases the thread utilization from 20 to 89 % without any thread synchronization. The proposed encoder can make the portion of ME in the encoder negligible with 2.2 % bitrate increase against the HEVC test model (HM) encoder. In terms of ME, the proposed ME is 130.7 times faster than that of the HM encoder.

High Efficiency Video Coding (HEVC) is the latest video coding standard that supports high resolution videos by providing approximately twice the compression efficiency as compared to its previous standard H.264. Motion Estimation (ME) in HEVC is the most computation-intensive block as a result it becomes a bottleneck in the design of the encoder while implementing video applications on various computing platforms such as general purpose and embedded processors. So developing computational efficient architectures on Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) platforms is inevitable. This paper proposes a fast hybrid search pattern algorithm and its hardware architecture for encoding UHD videos. The proposed Integer ME (IME) algorithm requires an average of 11.19% less encoding time than the default Test Zone Search (TZS) algorithm in HM reference software with compromising decrement in PSNR and increment in bit rate. The proposed architecture is implemented in both FPGA and ASIC platform with TSMC 90 nm technology library. It consumed 32-33% of resources in Virtex-7 FPGA and 2784.4 K equivalent gate count (in terms of NAND ) and 18 kB of memory, respectively. The results show that maximum frequency of the proposed architecture is 162 MHz and a total power consumption is 463.4 mW. The architecture provides a maximum throughput of 2.78 Gpixels/sec due to it process $$32\times 32$$ CU comparatively much less clock cycles (59.5) as compared to the state-of-the-art literature . Further, it supports 8K UHD $$(8192\times 4320)$$ @ 78 fps.

Modern video coding standards such as High Efficiency Video Coding (HEVC) and H.264/MPEG‐4 advanced video coding (AVC) supersede the previous coding standards because of their improved coding efficiency. These standards adopt variable block sizes in frame coding ranging from 4 × 4 to 16 × 16 and 4 × 4 to 64 × 64 for H.264/AVC and HEVC, respectively. The use of variable block sizes for inter prediction provides a significant coding gain compared to coding a macroblock (MB) using regular block size. However, this new feature greatly increases the computational complexity of the encoder when brute‐force rate distortion optimization (RDO) algorithm is used for coding parameter selection. This paper proposes an efficient inter prediction mode selection scheme based on motion homogeneity and residual complexity measures of an MB to speed up the encoding process. The motion homogeneity is assessed through the normalized motion vector (MV) field, and residual complexity is evaluated by the sum of absolute difference (SAD). To acquire the MVs and SADs, motion estimation at 8 × 8 block size is performed using a lightweight recursive motion estimator in which the vector field tends toward true object motion. Based on motion homogeneity and residual complexity of an MB, only a small number of inter prediction modes are selected for the RDO process. The experimental results for H.264/AVC show that the proposed scheme reduces the encoding time by 64% on average without any significant degradation of coding efficiency. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

The joint collaborative team on video coding (JCT-VC) is developing the next-generation video coding standard which is called high efficiency video coding (HEVC). In the HEVC, there are three units in block structure: coding unit (CU), prediction unit (PU), and transform unit (TU). The CU is the basic unit of region splitting like macroblock (MB). Each CU performs recursive splitting into four blocks with equal size, starting from the tree block. In this paper, we propose a fast CU depth decision algorithm for HEVC technology to reduce its computational complexity. In2N×2N PU, the proposed method compares the rate-distortion (RD) cost and determines the depth using the compared information. Moreover, in order to speed up the encoding time, the efficient merge SKIP detection method is developed additionally based on the contextual mode information of neighboring CUs. Experimental result shows that the proposed algorithm achieves the average time-saving factor of 44.84% in the random access (RA) at Main profile configuration with the HEVC test model (HM) 10.0 reference software. Compared to HM 10.0 encoder, a small BD-bitrate loss of 0.17% is also observed without significant loss of image quality.

A design for an integer motion estimator of high‐efficiency video coding (HEVC) is presented. HEVC supports the 64 × 64 coding tree unit, the recursive quad‐tree coding unit structure and the asymmetric motion‐partitioning mode in a high compression ratio. These features require a structure of integer motion estimation that is more complex than that of H.264/AVC. The new structures of a memory read controller and a sum of absolute difference (SAD) summation block are proposed. The new memory read controller reduces the internal memory read time, and the new SAD summation block structure supports the recursive quad‐tree coding unit structure and the asymmetric motion‐partitioning mode. The proposed design is implemented in Verilog HDL and synthesised using the 65 nm CMOS technology. The gate count is 3.56 M, and the internal static random access memory is about 20 kbyte. The operation frequency is 250 MHz when a 4 K‐Ultra high definition (UHD) (3840 × 2160P at 30 Hz) sized video is encoded.

The latest video coding standard High Efficiency Video Coding (HEVC) is developed by Joint Collaborative Team on Video Coding(JCTVC). HEVC can achieve better compression performance than any other coding standards, which adopts the quadtree structured coding tree unit (CTU). In encoding process, the CTU is recursively split into four equally sized coding unit (CU)s. Along with the multiple sizes of the CUs, the number of prediction unit(PU) modes has been largely increased, which raises the computational complexity in HEVC encoder greatly. In this paper, a fast inter mode decision algorithm based on motion estimation (ME) and texture feature is proposed to speed up the PU mode decision in HEVC encoder. Experimental results demonstrate that the overall algorithm that is proposed can save 41% encoding time on average while the decrease of coding quality is negligible, when compared to that of the HM10.0 reference software.

Although high efficiency video coding (HEVC) has achieved high coding performance, it has been shown that dependent rate-distortion optimization (RDO) can still further improve the coding performance at the encoder side. Inspired by our previous work on temporal-dependent RDO, this paper proposes a rate control method at coding tree unit (CTU) level to obtain both higher rate-distortion (R-D) performance and lower bitrate errors. We first formulate the global optimization problem in hybrid video coding and present a general solution framework based on a weighted Lagrange multiplier, where the weighted coefficient is related to the strength of temporal dependency among coding units, and a propagation factor is introduced for quantitative measurement of the temporal dependency. Second, an estimation method of CTU level R-D model is proposed to characterize R-D relationship more accurately. Finally, under the constraint of frame level bit budget, a formulation combining inter-block dependency and R-D characteristic is developed for optimal bit allocation at the CTU level. In the process of encoding a frame, a relaxed constraint algorithm (RCA) and a strict constraint algorithm (SCA) are employed to reduce the difference between numbers of actual and target bits for the current frame, respectively. Experimental results demonstrate that, on the HEVC test model (HM-16.7), our methods including RCA and SCA achieve considerable R-D performance improvement with lower bitrate errors, outperforming the state-of-the-art schemes. It is worth mentioning that even compared with HEVC without rate control, the RCA can still achieve bitrate savings of 5.4% and 5.1% on average under configurations of low delay P and B frames, respectively.

HEVC (high efficiency video coding), as the latest video coding standard, is more efficient than H.264/AVC, nevertheless it also brings in a very high computational complexity. To reduce the time of CU (coding unit) splitting or PU (prediction unit) mode deciding, a fast algorithm based on ANN (artificial neural network) and texture analysis is proposed in this paper. First, we acquire and then label the CUs of the training set with “split” and “unsplit” according to the quad-tree CU depth. Second, the texture features of “split” and “unsplit” CUs are quantified and compiled, based on which we can set the texture thresholds to judge whether or not to split the current CU or which prediction mode should be taken preliminarily. Finally, in terms of the CUs we can't judge from texture, we use ANN or the original algorithm of HM (HEVC test model) software to decide. Compared to HM15.0, the proposed algorithm can save 51.85% encoding time on average with negligible coding efficiency loss.

Objective appraisal method, for instance, sum of absolute difference (SAD) or sum of the squared errors (SSE), is adopted by high efficiency video coding (HEVC), which inherits conventional objective rate distortion model. However, these methods fail to achieve high consistency with subjective visual perception. In order to improve computational efficiency of the video coding in HEVC, in this article, structural similarity (SSIM) is considered as rate distortion cost function of HEVC. MSE is introduced into SSIM, so that a new rate distortion cost function can get. This problem can be solved by using the Lagrangian multiplier method. The simulation results showed that compared our proposed algorithm with HM13.0 in AI configuration, the performance of rate distortion is average improved about 2.6%, as well as getting better coding quality. In addition, no significant runtime increases in the stage of encoding.

The complexity of motion estimation in the High Efficiency Video Coding (HEVC) standard is very high as it uses a number of prediction block sizes. The test zonal search (TZS) mechanism is used as motion estimation algorithm in the fast search mode of HM encoder, the reference software for HEVC. In this paper, we present schemes for reducing the complexity of the TZS algorithm for uni-prediction in HEVC. The proposed mechanisms help in reducing complexity of grid, raster and refinement search stages of TZS. The performance of the proposed mechanisms is tested independently and also combined in the fast search mode of HM-16.18. The motion estimation time and the number of search points in the combined algorithm are reduced by 68.14% and 77.10% with a BD-rate of 0.30% and a BD-PSNR of $$-0.007$$ dB in comparison with the original fast search mode in the low-delay P main profile. The proposed complexity reduction schemes are compared with those adopted in other recently proposed fast motion estimation algorithms and the performance of the proposed scheme is found to be superior in terms of the reduction in motion estimation time.