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  • https://doi.org/10.1145/123186.123311Copy DOI Icon

A hierarchy preserving hierarchical compactor

  • Jan 1, 1990
  • David Marple
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Abstract

This paper describes a one-dimensional compactor which simultaneously compacts the contents of all cells of a layout hierarchy without changing the hierarchy. The compactor performs both compaction and wire length minimization hierarchically using the power of the Simplex method for linear programs. Compaction of arrays, compaction of overlapping cells, and symmetry preserving compaction are also handled, since these are special cases of layout hierarchies. Using dedicated Simplex algorithms for compaction and wire length minimization, a globally optimum result is produced quickly and efficiently without the use of protection frames or domains and terminals. The compactor corrects design rule violations, preserves wire widths, and maintains terminal connections automatically. It does not yet introduce jogs in wires automatically. Results are provided for a few CMOS modules, including a ROM and an SRAM core.

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