A high-performance framework for a network programmable packet processor using P4 and FPGA

Building the machines that advance scientific knowledge is one of the most significant challenges of our time. So-called Big Science instruments are unique; the expertise required to build them is multidisciplinary, and few countries can build and maintain them. Since resources and budgets are not unlimited, these require efficient solutions. Big Science machines take a decade to plan, a decade to build, and at least a decade to operate. One such machine is the largest fusion reactor project, ITER, which promises to be the next step in fusion research and has a big challenge in system integration. To mitigate the integration effort, ITER has invested in standardization, both in software and hardware, introducing standard instrumentation software named Nominal Device Support (NDSv3); Micro Telecommunication Computing Architecture (MTCA) as the long-term hardware standard choice, and EPICS as a general-purpose distributed control system. These control systems are essential in the management of the facility. They provide functions such as communication protocols, process management, monitoring, alarms, and human-machine interfaces. But also, more advanced access to databases or data acquisition systems. The latter is typically managed by a Field Programmable Gate Array (FPGA), of which facilities can easily have thousands of these FPGAs managing millions of signals within the control system environment. Nevertheless, these FPGA data acquisition (DAQ) systems continue to be labor-intensive. Standardized, modular, and open-source frameworks have been proposed to solve this problem, however, the FPGA programming expertise requirement remained. This thesis proposes a complete technology stack that considers these DAQ systems from the control system to the hardware. It provides a methodology using the Open Computing Language (OpenCL) to reduce the FPGA programming effort. The FPGA devices are programmed using C/C++-like environments, which are much simpler than traditional Hardware Description Languages (HDLs). The software, named IRIO-OpenCL, is written in C++ following ITER's NDSv3 model, which abstracts and generalizes the development of software device drivers and simplifies the interface to EPICS. IRIO-OpenCL is specifically designed to simplify the integration of intelligent instrumentation systems, allowing the integration of algorithms into the FPGA without modifying large parts of the supporting library. The MTCA standard was chosen to maintain modularity. The chassis backplane connects to the devices via Ethernet and PCIe, enabling standard communications. The Advanced Mezzanine Card is the typical MTCA FPGA-based DAQ carrier board. It connects the FPGA to the chassis backplane and typically provides FPGA Mezzanine Connectors (FMCs) for plugging in analog-to-digital (ADC) carrier boards. An ADC connected via the FMC interface samples the analog signals passed to the OpenCL processing kernels. Using OpenCL, the FPGA kernels communicate with the host machine in a standardized way. To demonstrate the applicability of this methodology, reference problems were selected from the literature and implemented, both with traditional and deep learning (DL) solutions. The methodology elaborates on connecting the OpenCL kernels for any use case, and the results show examples of kernel sets. The neutron flux measurement problem is solved at 1GS/s in real time using pulse counting and Campbell techniques, using 40% of the target Arria10 FPGA. The DL application example is based on a neutron/gamma discrimination neural network (NN) that achieves a classification rate of up to 1.3 MEvents/s using less than 25% of the target resource. RESUMEN Construir máquinas que avancen el conocimiento científico es uno de los desafíos más significativos de nuestro tiempo. Los instrumentos de la llamada Big Science son únicos; las competencias requeridas para su construcción son multidisciplinares, y pocos países pueden construirlos y mantenerlos. Dado que los recursos y presupuestos no son ilimitados, estos requieren soluciones eficientes. Las máquinas de Gran Ciencia tardan una década en planificarse, una década en construirse y al menos una década en operarse. Una de estas máquinas es el proyecto del reactor de fusión más grande, ITER, que promete ser el siguiente paso en la investigación de fusión y presenta un gran desafío en la integración de sistemas. Para mitigar el esfuerzo de integración, ITER ha invertido en estandarización, tanto en software como en hardware, introduciendo un software de instrumentación estándar llamado Nominal Device Support v3 (NDSv3); Micro Telecommunication Computing Architecture (MTCA) como la elección estándar de hardware a largo plazo, y EPICS como un sistema de control distribuido de propósito general. Estos sistemas de control son esenciales en la gestión de la instalación ya que proporcionan funciones como protocolos de comunicación, gestión de procesos, monitorización, alarmas e interfaces de usuario, además de acceso avanzado a bases de datos o sistemas de adquisición de datos. Este último es típicamente gestionado por un Field Programmable Gate Array (FPGA), de los cuales las instalaciones pueden tener fácilmente miles de unidades gestionando millones de señales dentro del entorno del sistema de control. Estos sistemas de adquisición de datos (DAQ) con FPGA siguen requiriendo programación experta y laboriosa. Se han propuesto marcos estandarizados, modulares y de código abierto para resolver este problema, sin embargo, la necesidad de experiencia en programación FPGA no se ha podido eludir. Esta tesis propone una pila de tecnologías que considera estos sistemas DAQ desde el sistema de control hasta el hardware. Proporciona una metodología utilizando el Open Computing Language (OpenCL) para reducir el esfuerzo de programación FPGA. Los dispositivos FPGA se programan utilizando entornos similares a C/C++, que son mucho más simples que los Lenguajes de Descripción de Hardware (HDL) tradicionales. El software, llamado IRIO-OpenCL, está escrito en C++ siguiendo el modelo de NDSv3 de ITER, que abstrae y generaliza el desarrollo de controladores de dispositivos de software y simplifica la interfaz con EPICS. IRIO-OpenCL está específicamente diseñado para simplificar la integración de sistemas de instrumentación inteligentes, permitiendo la integración de algoritmos en el FPGA sin modificar grandes partes de la biblioteca de soporte. El estándar MTCA fue elegido para mantener la modularidad. El backplane del chasis se conecta a los dispositivos a través de Ethernet y PCIe, habilitando comunicaciones estándar. La Advanced Mezzanine Card es la placa portadora DAQ FPGA típica de MTCA, que conecta el FPGA al backplane del chasis y típicamente proporciona FPGA Mezzanine Connectors (FMC) para conectar placas con conversores analógico-digitales (ADC). Un ADC conectado a través de la interfaz FMC muestrea las señales analógicas pasadas a los núcleos de procesamiento OpenCL. Utilizando OpenCL, los núcleos FPGA se comunican con la máquina anfitriona de una manera estandarizada. Para demostrar la aplicabilidad de esta metodología, se seleccionaron e implementaron problemas de referencia de la literatura, tanto con soluciones tradicionales como de Deep Learning (DL). La metodología elabora ejemplos de conexión de núcleos OpenCL para cualquier caso de uso, y los resultados muestran ejemplos de conjuntos de núcleos. El problema de medición del flujo de neutrones se resuelve a 1GS/s en tiempo real utilizando técnicas de conteo de pulsos y Campbell, utilizando el 40% del objetivo FPGA Arria10. El ejemplo de aplicación DL se basa en una red neuronal para la discriminación neutrones/gammas que logra una tasa de clasificación de hasta 1.3 MEventos/s utilizando menos del 25% de la FPGA objetivo. LABURPENA Ezagutza zientifikoa aurreratzen duten makinak eraikitzea gure garaiko erronka garrantzitsuenetako bat da. Big Science deritzonaren makinak bakarrak dira; beharrezko esperientzia diziplina anitzekoa da, eta herrialde gutxik eraiki eta mantendu ditzakete. Baliabideak eta aurrekontuak mugagabeak ez direnez, konponbide eraginkorrak behar dira. Zientzia Handi makinak hamarkada bat behar dute diseinatuak izateko, hamarkada bat eraikitzeko eta gutxienez hamarkada bat jarduteko. Makina horietako bat fusio-erreaktore handienaren proiektua da, ITER, fusio-ikerketan hurrengo urratsa izango dena eta sistemak integratzeko erronka handia aurkezten duena. Integrazio-ahalegina arintzeko, ITERek estandarizazioan inbertitu du, bai softwarean bai - eta EPICS helburu orokorreko kontrol-sistema banatua. Kontrol-sistema horiek funtsezkoak dira instalazioa kudeatzeko. Komunikazio-protokoloak, prozesuen kudeaketa, monitorizazioa, alarmak eta pertsona-makina interfazeak bezalako funtzioak ematen dituzte, datubaseetarako edo datuak eskuratzeko sistemetarako sarbide aurreratua izateaz gain. Azken hori "Field Programmable Gate Array" (FPGA) batek kudeatzen du, milaka FPGA konektatuz makina bakoitzean eta kontrol-sistemaz milioika seinale kudeatuz. FPGA duten datuak eskuratzeko sistemek (DAQ) programazio aditua eta neketsua eskatzen jarraitzen dute. Problema hori ebazteko marko estandarizatuak, modularrak eta kode irekikoak proposatu dira, hala ere, FPGA hardware programazio espezializatuaren beharra ezin izan da ukatu. Tesi honek DAQ sistema hauek kontrol sistematik hardwareraino kontsideratuz teknologia bilduma bat programazio-ahalegina murrizten du. FPGA gailuak C/C++ antzeko inguruneak erabiliz programatzen dira, - OpenCL izenekoa, C++n idatzita dago, ITERren "Nominal Device Support v3" (NDSv3) eredua jarraituz. Honek software-gailuen garapena diseinu abstraktu eta orokorrez EPICSekiko interfazea sinplifikatzen du. IRIOOpenCL berariaz diseinatuta dago instrumentazio-sistema adimendunen integrazioa sinplifikatzeko, eta algoritmoak FPGAn integratzea ahalbidetzen du, software zati handiak aldatu gabe. Modularitateari eusteko, MTCA estandarra aukeratu da. Txasisaren backplanea Ethernet eta PCIe bidez konektatzen da gailuetara, komunikazio estandarrak gaituz. "Advanced Mezzanine Card" MTCAren ohiko DAQ FPGA plaka eramailea da. FPGA txasisaren backplanera konektatzen du eta, normalean, "FPGA Mezzanine Connectors"ak (FMC) ditu plaka bihurgailu analogiko-digitalak (ADC) konektatzeko. ADCak, FMC interfazearen bidez konektatuta, OpenCL prozesatze-nukleoetara igarotako seinale analogikoak bihurtzen ditu. OpenCL erabiliz, FPGA nukleoak ordenagailuarekin modu estandarizatuan komunikatzen dira. Metodologia horren aplikagarritasuna egiaztatzeko, erreferentziazko adibideak literaturatik hautatu eta nukleoen konexio-adibideak egiten ditu, edozein kasutan erabiltzeko, eta emaitzek nukleo multzoen adibideak erakusten dituzte. Neutroi-fluxuaren neurketak 1GS/s-ko ebazten dira real time errendimenduaz, pultsuak eta Campbell zenbatzeko teknikak erabiliz, Arria10 FPGAren % 40 erabiliz. Azkenik, DL aplikazioaren adibidea, neutroi/gamma sailkapena, sare neuronal batean oinarritzen da, eta FPGAren baliabideen % 25 baino gutxiago erabiliz 1.3 MSailkapen/s sailkapen-tasa lortzen du.

Background: In recent years, the rising demand for high-performance radar systems in aeronautics, astronautics, national defense, and civil communication has driven the widespread application of phased-array technology. The design of beam controllers, the core of phased-array systems, faces many challenges. Traditional implementation schemes are usually based on application-specific integrated circuits (ASIC) or discrete components, which have a long development cycle, poor flexibility, and limited adaptability. Field-programmable gate arrays (FPGA), with their high parallelism, reconfigurability, and powerful signal processing capabilities, offer a new way to implement phased-array control systems. But FPGA design has traditionally relied on register transfer level (RTL) description, which is inefficient and struggles to keep up with the rapid iteration of complex algorithms. With the development of high-level synthesis (HLS) technology, it has become possible to develop FPGAs using high-level languages such as C/C++. However, improving development efficiency while ensuring hardware performance remains a key issue in the design of phased-array beam controllers. Materials and Methods: This study employs an HLS - RTL co - design method to build a phased - array beam controller. This approach combines the strengths of HLS's efficient algorithm implementation and RTL's precise hardware interface control. The system architecture consists of three parts: the host - machine control layer, FPGA processing layer, and phase - control output layer. In the FPGA processing layer, the core beam - forming algorithm is implemented via HLS. Based on phased - array principles, this algorithm converts target angles to wave vectors and calculates phase - compensation values for each element in an 8×8 array. Pipelining and parallel processing techniques are used in the HLS design to optimize algorithm throughput and latency. The phase - control output layer, designed with RTL, repackages 64 calculated phase values and distributes them to 16 physical phase - shifter chips. Each phase - shifter manages four elements and receives control data through an SPI interface. Results: The proposed FPGA-based phased-array beam controller design in this paper has successfully achieved high - speed, high - precision beam control. By using the HLS - RTL co - design method, it has solved the problem of low algorithm implementation efficiency in traditional FPGA development and ensured the high performance and reliability of hardware interfaces. Experimental results indicate that the system meets or surpasses design targets on key performance indicators. Its end - to - end latency is kept within 130μs, it supports an angle update rate of over 5,000 times per second, and can satisfy the requirements for tracking highly dynamic targets in practical applications. Conclusion: The major contributions of this research are as follows: presenting an HLS - RTL co - design methodology for complex FPGA system development; designing an efficient phased - array beam - forming algorithm and its hardware implementation; and developing a flexible and scalable phased - array control system architecture that supports different array configurations. These findings are highly significant for beamforming technologies in phased - array radar and 5G communication systems, as well as for other FPGA applications requiring high - speed signal processing.

This paper presents the simulation study of nonlinear dynamic of cardiac excitation based on Luo Rudy Phase I (LR-I) model towards numerical solutions of ordinary differential equations (ODEs) responsible for cardiac excitation on field programmable gate arrays (FPGAs). As computational modeling needs vast of simulation time, a real-time hardware implementation using FPGA could be the solution as it provides high configurability and performance. For rapid prototyping, MATLAB Simulink that offers a link with the FPGA has been used. Through Simulink HDL Coder, a tool in the MATLAB software that capable to convert the MATLAB Simulink blocks into hardware description language (HDL) code and an FPGA-in-the-loop (FIL) and co-simulation for verification, FPGA hardware implementation can be done. As a result, the LR-I excitation model is successfully simulated by using the MATLAB Simulink and the VHDL code has been successfully generated by the HDL Coder after fixed-point optimization is done. The FIL verification on actual FPGA board also has shown quantitatively comparable results to the MATLAB Simulink simulation. Therefore, the design flow has given a positive outlook in developing this FPGA stand-alone implementation.

In digital signal processing, digital down converters (DDCs) convert digitized, band-limited signals to lower frequency signals at a smaller sampling rate to simplify subsequent filtering stages. Software-defined radio (SDR) is a radio communication system in which components that are traditionally implemented in hardware are implemented in software on an embedded system. DDCs are widely used in modern communication systems, such as SDRs. Herein, we propose a low-power- and area-optimized implementation of a DDC for SDR applications. The DDC was designed using an innovative and novel high-level synthesis (HLS) design method based on application-specific bit widths for data nodes. The results achieved after a field programmable gate array (FPGA) implementation are superior to those obtained from hand-coded register transfer level (RTL) implementations in terms of area and power efficiency, with almost the same speed of operation. Our results were obtained using the MATLAB hardware description language (HDL) coder for HLS and Xilinx Vivado (a software for the synthesis and analysis of HDL designs) for synthesis. The DDC down-converts an input of 200 MHz signal to an output of 2 MHz signal. This implementation was conducted on a real FPGA hardware (Xilinx Kintex-7) and verified against the design specifications using an FPGA in the loop feature of HDL Verifier and MATLAB. In addition, we propose a generic methodology for improving the area, speed, and power for different application designs and HLS tools. The proposed methodology is also applicable to hand-coded RTL designs for any application.

This thesis work presents the implementation and validation of image processing problems in hardware to estimate the performance and precision gain. It compares the implementation for the addressed problem on a Field Programmable Gate Array (FPGA) with a software implementation for a General Purpose Processor (GPP) architecture. For both solutions the implementation costs for their development is an important aspect in the validation. The analysis of the flexibility and extendability that can be achieved by a modular implementation for the FPGA design was another major aspect. This work is based upon approaches from previous work, which included the detection of Binary Large OBjects (BLOBs) in static images and continuous video streams [13, 15]. One addressed problem of this work is the tracking of the detected BLOBs in continuous image material. This has been implemented for the FPGA platform and the GPP architecture. Both approaches have been compared with respect to performance and precision. This research project is motivated by the MI6 project of the Computer Vision research group, which is located at the Bonn-Rhein-Sieg University of Applied Sciences. The intent of the MI6 project is the tracking of a user in an immersive environment. The proposed solution is to attach a light emitting device to the user for tracking the created light dots on the projection surface of the immersive environment. Having the center points of those light dots would allow the estimation of the user’s position and orientation. One major issue that makes Computer Vision problems computationally expensive is the high amount of data that has to be processed in real-time. Therefore, one major target for the implementation was to get a processing speed of more than 30 frames per second. This would allow the system to realize feedback to the user in a response time which is faster than the human visual perception. One problem that comes with the idea of using a light emitting device to represent the user, is the precision error. Dependent on the resolution of the tracked projection surface of the immersive environment, a pixel might have a size in cm2. Having a precision error of only a few pixels, might lead to an offset in the estimated user’s position of several cm. In this research work the development and validation of a detection and tracking system for BLOBs on a Cyclone II FPGA from Altera has been realized. The system supports different input devices for the image acquisition and can perform detection and tracking for five to eight BLOBs. A further extension of the design has been evaluated and is possible with some constraints. Additional modules for compressing the image data based on run-length encoding and sub-pixel precision for the computed BLOB center-points have been designed. For the comparison of the FPGA approach for BLOB tracking a similar implementation in software using a multi-threaded approach has been realized. The system can transmit the detection or tracking results on two available communication interfaces, USB and RS232. The analysis of the hardware solution showed a similar precision for the BLOB detection and tracking as the software approach. One problem is the strong increase of the allocated resources when extending the system to process more BLOBs. With one of the applied target platforms, the DE2-70 board from Altera, the BLOB detection could be extended to process up to thirty BLOBs. The implementation of the tracking approach in hardware required much more effort than the software solution. The design of high level problems in hardware for this case are more expensive than the software implementation. The search and match steps in the tracking approach could be realized more efficiently and reliably in software. The additional pre-processing modules for sub-pixel precision and run-length-encoding helped to increase the system’s performance and precision.

FPGAs (Field-Programmable Gate Array) may offer higher performance than CPU architectures. Hardware Description Languages (HDL), such as VHDL and Verilog, which are traditionally used to program FPGAs, are known as hard to learn, to use, and to debug. Optionally, High Level Synthesis (HLS), such as OpenCL, allows developers to focus on the design of functions following a high-level software development flow, makes it easier to program FPGAs. This paper implements an image filter in the frequency domain on an FPGA board by using OpenCL, making the FPGA board an accelerator device to the host PC. The experiment results show that the filter implemented on the FPGA device can be optimized by pipelining the signal processing tasks onto the FPGA and reduce the I/O requirements between host PC and FPGA. The optimized FPGA implementation has higher performance than the image filter totally implemented on CPU.

The high processing speed and reconfigurable features of FPGA (Field-Programmable Gate Array) make it the first choice for acceleration chip. Currently, the CPU/FPGA hybrid architecture is a research hotspot in improving hardware processing speed. Many companies have investigated in related researches. However, the current researches have not solved the coordination problem between CPU and FPGA in this architecture. The Communication efficiency problem between CPU and FPGA is the key to the failure of hardware performance. Some of the current researches are mainly to optimize the communication protocol between CPU and FPGA to improve data transfer rate. This paper proposes a different method to reduce the frequency of communication between CPU and FPGA for this problem. The processing speed of the architecture is improved by simplify communication between the CPU and the FPGA. This approach reduces communication frequency between the CPU and the FPGA by splitting the software into hardware master thread and slave threads that can run independently run on the FPGA. The CPU only needs to configure the FPGA at the beginning and retrieve the result from the FPGA at the end. No communication is required during FPGA running, thereby reducing unnecessary communication waste.

To address the rate mismatch between high-bandwidth, high-sampling-rate analog-to-digital converters (ADCs) and low-bandwidth, low-sampling-rate baseband processors, digital signal processing techniques were employed to enable the parallel processing of broadband signals.The broadband signals were decomposed into multiple narrowband channels, facilitating parallel processing and frequency-selective analysis of signals.The validity of the principle was verified through MATLAB modeling.A digital channelization Register Transfer Level (RTL) model was constructed on a Field-Programmable Gate Array (FPGA) using Verilog Hardware Description Language (HDL), implementing a pipelined parallel processing mechanism.The computational efficiency in Fast Fourier Transform (FFT) operations was improved by optimizing the processing flow.A digital channelization receiver application test board was developed using a domestically produced FMQL45T900 FPGA as the core component.Practical applications confirmed the correctness of the approach, with significant improvements in power efficiency compared to methods reported in existing literature, thereby enhancing overall parallel processing performance.This method demonstrates broad applicability in fields such as military communications, broadcasting, radar navigation systems, and more.

One of the main challenges in Systems designs is the ability to integrate real time high fidelity models on suitable and feasible hardware platforms. Because of its inherited parallelism, FPGA (Field Programmable Gate Arrays) technology achieves sample rates which are typically faster than real time. This can be seen as the last line of defence against the increasing requirements given by high fidelity models. But as most of the FPGA applications are specialised and the FPGA toolsets do not support basic control systems blocks, designs are constructed and optimised manually. This leads to significant effort required in finding feasible hardware FPGA implementations. Therefore, the work in this paper describes how to automatically optimise the most time consuming process found in generic FPGA implementations: the optimisation of the pipelining process. This is constructed on a rigorous mathematical model and achieved using drag and drop floating point HDL (Hardware Description Language) control systems blocks, under System Generator, in Simulink.

Neural networks (NNs) are used in numerous applications such as audio–video processing and image classification. NNs can address the limitations of the traditional computer algorithms. Recently, the research utilizing field-programmable gate arrays (FPGAs) to implement NNs is on the rise due to low power dissipation, easy and fast reconfigurability offered by these platforms. This is due to the research and development efforts put into the design optimization to improve the throughput of FPGAs. The integration of appropriate hardware with advanced artificial intelligence (AI) software presents many challenges. This paper offers a generalized model of NNs on a FPGA device. In addition, it presents the design process for the high-level synthesis (HLS) tools to implement the project on FPGA. This paper shows the results of latency, timing, pre- and post-synthesis, implementation, and hardware utilization on Xilinx FPGA target device. In this paper, NN for XOR logic gate operation is performed and verified by using HLS tool, and FPGA implementation is proposed. The NN and backpropagation algorithm are developed in high-level programming languages like Python, Java, C, C++. The training part of the NN has been done by using open-source software Dev C++, and tuned weights are taken to Xilinx Vitis HLS. Simulation, synthesis, and implementation are performed by using Xilinx Vitis HLS and Vivado 2020.1 electronic design automation (EDA) tools. NN architecture with tuned weights is implemented on Xilinx ZYNQ FPGA target device. This paper shows that we were able to achieve latency in one clock cycle interval through pipeline and array partition.KeywordsHigh-level synthesis (HLS)Neural networks (NNs)Register transfer level (RTL)Field-programmable gate arrays (FPGAs)Systems on chip (SOC)Artificial intelligence (AI)Graphic processing units (GPUs)Generalized NNs (GNN)Recurrent neural network (RNN)Feed-forward neural networks (FFNNs)

In real-time image processing, the demand for efficient solutions has surged with the proliferation of applications spanning from autonomous vehicles to medical diagnostics. This study addresses the imperative need for accelerated machine learning algorithms to enhance the processing speed of image-related tasks. The research focuses on leveraging Field-Programmable Gate Arrays (FPGAs) to implement hardware acceleration, exploiting their parallel computing capabilities. The advent of machine learning in image processing has revolutionized various industries, yet real-time applications encounter computational bottlenecks. This research delves into hardware acceleration using FPGAs to overcome these constraints, offering a novel approach to expedite machine learning algorithms. Traditional software implementations of machine learning algorithms often fall short in meeting real-time processing requirements. This research aims to bridge this gap by exploring FPGA-based hardware acceleration, addressing the performance limitations hindering the seamless integration of machine learning into real-time image processing systems. While existing literature acknowledges the potential of FPGA-based acceleration, a comprehensive exploration of its application for real-time image processing is lacking. This research fills the void by presenting a detailed method and empirical results, contributing to the limited body of knowledge on FPGA-accelerated machine learning in the of image processing. The study employs a systematic approach, integrating machine learning algorithms onto FPGAs through hardware description languages. The implementation is optimized to exploit parallelism inherent in FPGAs, resulting in a tailored hardware solution for real-time image processing. Comparative analyses against software implementations provide insights into the performance gains achieved. The experimental results demonstrate a significant enhancement in processing speed, validating the efficacy of FPGA-based hardware acceleration for machine learning algorithms in real-time image processing applications.

This paper explores the use of the Xilinx's system generator development tool for the implementation of control algorithms on Xilinx field programmable gate arrays (FPGA). The Simulink plug in complements traditional hardware description language (HDL) by providing a graphical language with a higher level of abstraction for the development of FPGA designs. After taking into consideration the challenges of converting control designs that have been implemented and verified within the Simulink environment to FPGA hardware implementation, a systematic approach is presented. As a case study, a FPGA implementation of a control system was derived and verified for a simulated unmanned ground vehicle (UGV). The design example demonstrates the validity of the presented method as an efficient and reliable method for rapid system prototyping for designs developed using the Simulink environment.

Industrial designers and educators who plan to design microelectronic systems (e.g. hardware accelerators, co-processors, etc.) are increasingly capturing their designs using hardware description languages such as VHDL and Verilog. The designs are then most often synthesized into programmable logic components such as field-programmable gate arrays (FPGAs) offered by Xilinx, Altera, Actel and others. This approach places the emphasis on high-level design which reduces time to market by relying on synthesis software and programmable logic to produce working prototypes rapidly. These prototypes may then be altered as requirements change or converted into high-volume mask gate arrays or other application-specific integrated circuits (ASICs) when the demand is known to be sufficient. These ASICs, however, must be designed to be testable to screen out those with manufacturing defects. Hence, scan logic must be inserted, test vectors generated and fault grading performed to ensure a high level of testability. These efforts complicate and delay the conversion of FPGA designs to ASICs but must be considered by designers of microelectronic systems. Topics covered include: design flow; system partitioning; hardware description languages (HDLs); specifying behavioral control; specifying structural components; critical paths; placement and routing; technology choices; FPGA applications; rapid prototyping; retargeting; manufacturing defects; scan chain insertion; test vector generation; fault grading, and ASIC production

Field-Programmable Gate Arrays (FPGAs) are becoming an interesting component for heterogeneous computing systems in the post-Moore era thanks to their reconfigurable nature. The current generation of FPGAs includes specialized hard blocks for floating point operations, making them attractive for scientific computing. FPGA programming has historically been done in hardware description languages, which required a deep understanding of hardware design. Emerging high-level synthesis tools, such as Intel oneAPI and AMD Vitis™, provide a more common programming environment for FPGAs. In this paper, we explore the capabilities of FPGAs for acceleration in the context of nuclear particle transport simulators. As a case study, we implement XS-Bench in Intel oneAPI targeting FPGAs, including basic optimizations. We then compare the performance of Intel Stratix10 FPGA and Intel Xeon CPU-based systems and evaluate the viability of FPGA use in heterogeneous systems.

In this paper, we describe the multiple biometric recognition system based on 32 bit floating-point digital signal processor (DSP) and field programmable gates array (FPGA). In addition, it has the function of real-time display, which can help the users easily capture the perfect image that they need. Different from other platforms of using DSP and FPGA, we have two kinds of parallel bus interfaces between them, the EMIF and HPI interface. With the help of the Hardware Description Language (HDL) Verilog HDL, we make it true that the DPS and FPGA can co-process the matching algorithms. Comparing with the matching time that processes only by the DSP, the co-processing is more efficient than the processing only by one processor. Besides, we leave several parallel and series interfaces in our board for the future use. Therefore, our system can be applied to many different digital signal processing domains and provide them an excellent computing platform.