A high-performance interface ASIC for quartz vibrating gyroscope

The JCSAT 9 Communications Satellite, developed by Lockheed Martin Commercial Space Systems using an A2100 [1] spacecraft, will use an on-orbit configurable Frequency Generation Unit (FGU) that is SEU hard and total dose tolerant. The spacecraft is due for launch in 2005. The FGU design [2] illustrates the principles and benefits of a single loop synthesizer generating low noise and multiple local oscillators for various frequency (up/down) converters in the payload. Nineteen phase-locked loops are configured to provide coherent, multiple, and redundant C and L band local oscillator frequencies by combining digital, analog and microwave concepts to achieve small size, low mass, low DC power consumption, low phase noise, and spectral purity.

The trend in the modern weapon development is to bind individual samples with a certain autonomy degree into a complex typically using wireless sensor networks. The scope of the complexes is indefinite and poorly formalized environments. It is possible to achieve the desired efficiency of such complexes mainly by improving the intellectual component of their control system and a separate unit in particular. However, it should be noted that the vast majority of research in this area remains at the theoretical level. There is a gap between primitive behavior models of artificial entities, for example in swarm robotics, models of their interaction and expectations from practice. The situation is aggravated by the requirements of secrecy, miniaturization, and low power consumption. The work objective is to propose an approach to developing software for intelligent control systems for a separate network node with a given autonomy degree in performing tasks. To propose relatively simple algorithms for giving a network node the intelligent behavior properties under power consumption and speed restrictions; to provide the ability to study the situation and make decisions, both independently taking into account the data received from other network devices and as part of a group. Methods. The paper uses the methods of fuzzy set theory, the theory of building fuzzy models and networks, as well as approaches and algorithms for building on-board intelligent control systems. Results. It is shown that the required algorithms can be developed after identifying typical situation classes and successful action methods in real conditions. This basis makes it possible to develop formal behavior models (patterns) for implementation in the node management system.

With the popularity of portable electronic devices, the demand for 12-bit low-power analog-to-digital converter (ADC) chips continues to grow. Considering that these devices typically rely on battery power, high precision and stability are crucial. In order to improve the voltage resistance of ADC chips under high voltage, an innovative bootstrap sampling switch design is proposed, which utilizes the capacitance characteristics of NMOS and PMOS transistors to enhance the voltage resistance of the chip. At the same time, considering factors such as power fluctuations, time domain and voltage interleaving, a two-stage hybrid architecture based on successive approximation registers (SARs) and time to digital converters (TDCs) was studied and designed to optimize the balance between low power consumption and high voltage resistance performance. The results showed that the power consumption of the chip design was only 9.5 mW. The voltage compensation measures significantly reduced the error value from 7.01% to 1.97%, optimizing 5.04%. In summary, this design not only improves the accuracy and speed of ADC chips, but also successfully controls the exponential growth of power consumption, which has strong practical value. The proposed solution by the research institute has broad potential in multiple application fields, especially suitable for situations with high requirements for power consumption and stability, such as medical imaging and aerospace. This design provides new ideas and directions for the development of high-performance and low-power ADC chips in the future.

Electricity is the symbol of modern industrial civilization, the basic input of production and the necessities of people’s life. With the development of economy, the electric power industry plays an increasingly important role in the national economy. Accurate judgment of power demand is the premise of scientific planning, and its basis is a correct understanding of the law of power consumption, as well as a scientific understanding of the inherent relationship between power demand and economic development. Therefore, this paper systematically studies the relevant data of China from 1993 to 2018, carefully analyses the relationship between economic development and power consumption, reveals the basic law of power consumption and economic development, and on this basis, sets up different scenarios around industrial structure and power consumption structure, and makes multi-scenario prediction of China’s electricity demand in the coming 2020, 2030 and 2050 years, with a view to providing China’s electricity demand. Force demand planning and related policy formulation provide some reference.

Background: Fast Fourier Transform (FFT) processor is the important method in Orthogonal Frequency Division Multiplexing (OFDM) communication systems. Split-Radix Fast Fourier Transform (SRFFT) estimates the least number of multiplications compared to other FFT algorithm; hence SRFFT is the best for the implementation of low power FFT processor. Methods: In this paper, the proposed “pipelined 32-point Split-Radix Multi-path Delay Commutator (SFMDC) FFT” architecture is designed. The MDC architecture has advantages in reducing the low chip area and lower power consumption. The SR-FFT algorithm has changing the numbers of butterfly elements in successive stages. The 32-point SR-MDC FFT architecture is to determine the frequency transformation techniques. The Split-Radix FFT algorithm is based on radix-2 and radix-4 algorithm and it is related to mixed radix FFT. Findings: The performance evaluation of proposed architecture is determined through VLSI System. Less area, low power consumption and high speed are the main parameters in this design. The proposed structure provides high throughput rate and low hardware complexity. Improvements: The goal of this proposed work is to reduce the slices and LUTs and power consumption and also to enhance the performances of the FFT processor than the existing method. The proposed method has been evaluated by using ModelSim 6.3C and synthesis results has been validated by using Xilinx Plan ahead 12.4.

We have proposed a memory based recursive FFT design which has much less gate counts, lower power consumption and higher speed. The proposed architecture has three main advantages (1) fewer butterfly iteration to reduce power consumption, (2) pipeline of radix-22 butterfly to speed up clock frequency, (3) even distribution of memory access to make utilization efficiency in SRAM ports. In summary, the speed performance of our design easily satisfies most application requirements of Fixed 802.16d and Mobile 802.16e WiMAX, which uses OFDMA modulated wireless communication system. Our design also occupies lesser area, hence lower cost and power consumption.

Smart sensor network technology integrates sensors, embedded computing, modern networks, wireless communication and distributed information processing technologies, and is currently a frontier hot research field in the world. The application of wireless sensor network to the greenhouse environment monitoring system to realize self-organizing network, wireless data transmission and intelligent control is also of great significance to the realization of agricultural modernization. The purpose of this paper is to study the monitoring of macadamia nut planting environment based on smart sensor technology. Since the greenhouse environment monitoring system has very high requirements for power consumption, cost and stability, this article selects ZigBee wireless sensor network technology with low power consumption, low cost, high stability, etc. to build a set of monitoring temperature and humidity Greenhouse wireless smart sensor network model. According to the actual requirements of greenhouse environment monitoring, this article proposes a new type of ZigBee technology-based greenhouse macadamia nut planting environment monitoring system solution, and gives the overall structure of the system. Considering many aspects such as cost and power consumption, this article stores, displays, analyzes and processes the acquired data. The functions of the system meet the design requirements. The system realizes the collection of greenhouse parameters and the data display and processing functions, and realizes the video monitoring of the greenhouse. Experimental studies have shown that in the actual greenhouse environment, due to a large number of crops blocking, it is bound to produce certain obstacles to signal transmission, but because of the large number of nodes, the distance between the node and its parent node will not exceed 25m, which also ensures The data collected by sensor nodes can be safely and error-freely transmitted to the coordinator node in a multi-hop manner.

Refrigerated infrared focal plane detectors are widely used in military equipment and astronomical detection fields due to their advantages of high detection accuracy, long detection distance and short response time. The preamplifier circuit mainly receives and amplifies the weak signal of the detector, and its signal processing effect directly affects the imaging quality of the detector. Based on SMIC 180nm CMOS technology, an operational amplifier with low power consumption and high gain is designed to meet the requirements of the preamplifier circuit of the cooled infrared detector for the working environment and performance.We mainly analyze the low-temperature characteristics and circuit principle of CMOS,further simulation and testing was also performed. Simulation test results reveal that the operational amplifier has an open-loop gain of 124dB, and its power consumption is only 4.75mW when driving 200-400PF under heavy load. Under the premise of low noise, it can well meet the requirements of lower power consumption, high gain and load capacity of the pre-amplifier circuit of the refrigerated infrared detector. It can be widely used to readout infrared (IR) sensors and focal plane imaging arrays (FPA).

Introduction Single atom catalysts have draw increasing attention of enormous researchers due to its atomically disperation on supports, high efficiency and high catalytic performance. Despite those obvious advantages, there is still rare study about the single atom catalyst’s application in sensors. It was firstly reported the palladium single atoms on TiO2 used as a photocatalytic sensing platform to analyzed organophosphorus pesticide chlorpyrifos[1]. Catalyst-based sensing platform opens up a new pathway for exploring novel strategy of design sensors. Micro-electro-mechanical system (MEMS) process have advantages such as, miniaturization, small size, mechanical parts high resonance frequency, and low power consumption. However, the MEMS prepared by traditional method possess poor stability. Here, we employed the atomic layer deposition to prepare ZnO layer on MEMS. Atomic layer deposition (ALD) is a powerful technique for depositing nanoparticles or thin films and has outstanding advantages, including precise control of size and thickness and excellent uniformity[2], except that the substrate is exposed separately to each gaseous precursor and that the deposition is broken into cycles[3]. ALD functionalized method could gain high performance in thermal stability, mechanical and catalytic performance[4]. It was interesting to obtain single atom MEMS sensors via ALD. Method Prior to ALD, MEMS (Shanghai lingpan Electronic Technology Co., Ltd) were put into ethanol and cleaned by ultrasonic agitation for ten minutes. MEMS were put on quartz wafers and dried in air. ZnO films were deposited onto the MEMS by a hot-wall, closed-chamber ALD reactor. N2 (99.999%) was used as carrier gas. The precursors of ZnO were diethyl zinc and water (H2O). Water acts as an oxidant and enables growth over a wide temperature range. The deposition temperature was 150 °C, and the diethyl zinc was kept at room temperature. After the deposition of ZnO layers, Pt single atoms ALD was subsequently deposited with (methylcyclopentadienyl)trimethylplatinum (MeCpPtMe3) and O3 as precursors at the same temperature as our precious work[2]. Ultimately, the MEMS sensors were tested. Results and Conclusions Fig.1 Response performance for ALD SnO2 layer on MEMS It can be seen from the Fig.1 that sensor response increased with the concentration increase gradually. With the concentration increase for about 1 PPM, response value of sensors gradually reduced. It could also be seen that ALD ZnO sensor have a response time of 90 s and recovery time of 120 s. Baseline with drift less than 4 also demonstrated its good stability. It has little increase in response performance as the concentration increased to 80 PPM, it could be caused by the surface electron transfer arrived balance within high concentrations References [1] X. Ge, P. Zhou, Q. Zhang, Z. Xia, S. Chen, P. Gao, Z. Zhang, L. Gu, S. Guo, Palladium single atoms on TiO2 as a photocatalytic sensing platform for analyzing organophosphorus pesticide chlorpyrifos, Angew Chem Int Ed Engl, (2019).[2] Q. Hu, S. Wang, Z. Gao, Y. Li, Q. Zhang, Q. Xiang, Y. Qin, The precise decoration of Pt nanoparticles with Fe oxide by atomic layer deposition for the selective hydrogenation of cinnamaldehyde, Applied Catalysis B: Environmental, 218 (2017) 591-599.[3] Z. Gao, Y. Qin, Design and Properties of Confined Nanocatalysts by Atomic Layer Deposition, Acc Chem Res, 50 (2017) 2309-2316.[4] M.M. Biener, J. Biener, A. Wichmann, A. Wittstock, T.F. Baumann, M. Baumer, A.V. Hamza, ALD functionalized nanoporous gold: thermal stability, mechanical properties, and catalytic activity, Nano Lett, 11 (2011) 3085-3090. Figure 1

Audio extraction systems have important applications in the field of UAVs,especially in the areas of disaster emergency response, environmental monitoring and precision agriculture. However, the large size and high power consumption of existing systems limit their widespread use. In this study, a UAV information acquisition and transmission method based on low-power sensing and 4G remote transmission technology is proposed, aiming to achieve efficient processing and transmission of audio data while meeting the requirements of miniaturization and low power consumption.The system adopts a modular design and achieves low power consumption and efficient data transmission by optimizing the collaborative work between the front-end hardware and the back-end cloud platform. Experimental results show that the system exhibits high stability and significant low power consumption in complex environments (the lowest power consumption is 0.1mW), while the transmission efficiency is significantly improved over traditional methods (the average rate reaches 4.5Mbps).This study provides reliable technical support for the application of UAVs in complex missions.

With the rapid growth of traffic and power consumption in information and communication technology industry for decades, improving energy efficiency has become a challenging issue in recent years. Especially, the pervasive access to Internet via mobile devices will cause wireless traffic volume increment by 1000+ times in near future, which is expected to be carried by the fifth generation ultradense cellular network. Following this trend, the core network where optical fibers are deployed to deliver aggregated traffic needs upgrading to accommodate the increasing traffic volume. To match with the traffic growth rate, we should conduct efficient network planning over multiple time periods. Moreover, considering the heterogeneity in the bandwidth requirements among various network services, flexible mixed line rate scheme is adopted in network provisioning. In this paper, we study the long‐term multiperiod planning of optical core network by considering the traffic growth with the objective of high energy‐efficiency. Three planning strategies, say All‐period, Incremental, and End‐of‐Life, respectively, are studied and formulated as mixed integer linear programming models with the objective to minimize power consumption of optical core network. Given the estimation on the reduction of power consumed by various network devices, we can deploy network devices flexibly in each period through the optimization models. Performance of the proposed models is also evaluated and compared via case studies.

Speech trigger and speech command recognition technologies have become pivotal human-machine interfaces for AIoT applications. Typically, a speech-related system consists of a mel-filter-based handcrafted feature extractor and an artificial neuron-based classifier. Recent advancements [1–3] have demonstrated promising results by training the feature extractor jointly with the neural network classifier. Moreover, the emergence of spiking neuron network training algorithms and hardware designs has showcased their competitive edge over traditional artificial neural networks. Consequently, the design and training of learnable audio feature extractors and spiking neural network classifiers are the key focuses of this thesis. The first focus of this thesis is the design of an ultra-low-power, learnable audio feature extractor to support end-to-end training. Conventional low-power approaches, such as extreme pruning and quantization in the audio feature extractor (AuFEx) design, often result in decreased accuracy. To address this, the thesis proposes a hardware-aware, end-to-end training framework to co-optimize the AuFEx design, achieving high performance with minimal hardware cost. Two types of AuFEx designs are explored: a time-domain (TD) filter-based learnable audio feature extractor (AuFEx-TD) and a frequency-domain (FD) filter-based learnable audio feature extractor (AuFEx-FD). Using this framework, the AuFEx-TD achieves high accuracy (97.8%) for one wake word detection, with low power consumption (496 nW) and low latency (375 μs). The optimized AuFEx-FD demonstrates noise-robust 10-keyword spotting accuracy (87.5%@5dB – 92.2%@20dB) with low power consumption (1.26 μW). Both AuFEx-TD and AuFEx-FD designs are implemented using UMC 40nm CMOS technology to validate the framework's effectiveness. For the speech trigger or wake word detection (WWD) task, power and latency are critical design considerations. This thesis presents a sub-μW spiking neural network accelerator with an 8 ms latency. The core WWD engine employs a spiking convolutional neural network (SCNN) model, leveraging sparse activation and addition-only operations within spiking neurons. The proposed SCNN model enhances the existing framewise incremental computation flow [4] by incorporating a spike processing unit (SPU), reducing system power and latency by 16.5% and 43.2%, respectively. Extensive quantization further reduces weight and activation precisions to 4-bit and 1-bit. Additionally, a power-gating mechanism, driven by an energy-based voice activity detection (VAD) module, further minimizes power consumption in random and sparse event (RSE) scenarios. Full chip simulation results show that the chip consumes only 110 nW, with a 2.15% false alarm rate and a 3.00% false reject rate in a 10% voice event stream test. It achieves state-of-the-art recognition accuracy of 99% and 96% for one and two wake word detection tasks, respectively. For speech command recognition or keyword spotting (KWS) tasks, robustness against noise and speaker accents is essential for user experience. This thesis explores both end-to-end training and on-device transfer learning to enhance KWS chip robustness with minimal power overhead. The proposed chip comprises three main blocks: the Learnable Audio Feature Extractor (AuFEx), the Spiking-DSCNN Core (SC), and the Transfer Learning Core (TLC). The AuFEx is an optimized AuFEx-FD, with the on-chip memory for storing FD-filter parameters replaced by an FD-filter parameter generator, reducing power consumption to 1.225 μW. The SC implements a spiking neural network (SNN) model using a Depthwise Separable Convolutional Neural Network (DSCNN) topology. Multi-level encoding in spiking neurons reduces simulation time, while the inherent activation sparsity of these neurons decreases power consumption and latency. The TLC supports both forward and backward propagation for a fully connected layer and softmax layer, enabling the KWS chip to adapt to environmental and user variations using minimal labeled data and weight updates. Fabricated in UMC 40nm CMOS technology, the chip achieves 10-keyword spotting accuracy ranging from 87.5% to 92.2% under background noise levels of 5dB to 20dB. Through on-device transfer learning, the chip can improve KWS accuracy on personalized datasets by 11.73%, using only a few examples per keyword and limited training epochs. The simulated power consumption of the chip in streaming inference mode is 10.26 μW at a 250 kHz clock frequency and 0.85V supply voltage. In conclusion, this thesis presents an end-to-end spiking neural network-based speech system for speech trigger (WWD) and speech command recognition (KWS) tasks. By integrating the AuFEx-TD and the SCNN accelerator, as described in the first and second parts of the thesis, a low-latency, sub-μW wake word detection system has been developed. In the final part, a noise-robust, personalized, few-μW-level speech command recognition ASIC is introduced, demonstrating the feasibility of high-performance, low-power AIoT speech interfaces.

Microelectronics mounted on a piezoelectric transducer: Method, simulations, and measurements

This paper introduces an ultra-wideband low noise amplifier (UWB LNA) with a new structure. The circuit for ultra-wideband wireless communication system receiver front end is based on TSMC 0.18-μm CMOS technology. In 3.1 ~ 10.6 GHz its simulation results are as follow: the input return loss (S11) is less than -13.4 dB, the output return loss (S22) is less than -12.4 dB, the maximum gain (S21) is 17 dB, the reverse isolation (S12) is less than -50 dB, the minimum noise figure NF is 4 dB, the maximum of input third order intermodulation point (IIP3) is about -5.3 dBm, the power consumption of the circuit is about 9 mW under 1.5 V operating voltage. This design of UWB LNA has advantage of wide working bandwidth, high gain, low power consumption, good noise performance, high linearity, excellent input and output impedance matching.

This paper presents the design analysis of a low-power wideband single-ended CMOS low-noise amplifier (LNA). The proposed topology is based on a modified current- reuse circuit, in which two-stage common-source (CS) amplifiers consume the same DC current and are isolated from each other by large MIMCAPs, which results in good performance with low power consumption. The proposed circuit achieves a bandwidth of 2.5 GHz, suitable for several wireless communication standards such as GSM, WLAN, and Bluetooth. In the first stage, a current-reuse circuit with shunt feedback is used to satisfy input impedance matching and signal amplification with minimal noise injection. A common source (CS) with a source follower circuit forms the second stage to improve the noise figure (NF), harmonic distortion, and output impedance matching. The proposed LNA is designed in 65 nm CMOS technology and covers a frequency range of 0.17–2.68 GHz. The proposed LNA achieves a maximum gain of 17.24 dB, a minimum NF of 2.67 dB, a maximum IIP3 of −14.9 dBm, and input and output return losses of less than −10 dB. The power consumption of the proposed LNA is 3.52 mW from a 1 V power supply, and the core area is 0.3 mm2.