A High-Precision Current-Mode Bandgap Reference with Nonlinear Temperature Compensation.

Ultra-low-power (ULP) sensor technologies for the future internet of things have presented challenges in ULP implementation of reference circuits while keeping traditional requirements of stable performance. For voltage reference circuits, as an essential block in SoCs to generate various internal supply voltages, the bandgap voltage-reference (BGVR) scheme has been widely used since it provides a well-defined value with strong immunity to process/voltage/temperature variations. Nanowatt-consuming BGVR circuits have been recently proposed using a capacitor network [4] and a leakage-based proportional-to-absolute-temperature (PTAT) circuit [5]. On the other hand, the current reference circuit that is required to set internal bias current still presents difficulties in achieving both stable performance and ULP consumption. The general approach to building a current reference is to use a BGVR with additional resistors for V-to-I conversion. Though it can provide a well-defined stable current reference, it also requires excessively large resistance for ULP consumption. Another approach is a CMOS-based current reference circuit that tries to make the exponential term in the subthreshold current equation constant or temperature-independent, hence reducing process and temperature dependencies. While CMOS reference circuits have achieved ULP implementations, the current is still determined by a number of process and design parameters, resulting in large sensitivity to process variations. This paper presents a sub-10nW bandgap-reference (BGR) circuit that implements both voltage and current references in one circuit. The BGR circuit is implemented with a 0.18µm CMOS process and generates voltage and a current references of 1.238V and 6.64nA while consuming 9.3nW. The voltage and current references show standard deviations of 0.43% and 1.19% with temperature coefficients of 26ppm/°C and 283ppm/°C, respectively.

The reference voltage is a core part of RFID tags, its performance directly determines the whole chip's life and performance. The temperature coefficient is one of the important performances of the reference voltage source and the high-order temperature compensation is an effective method to reduce the temperature coefficient of the reference source. A low temperature coefficient bandgap reference is designed based on the standard 65nm CMOS process, and the low-supply voltage operation with bandgap reference circuit with current mode structure. The designed CMOS bandgap voltage reference is in the range of -20°C to 100°C with temperature coefficient of 9.6 ppm/°C and provides a good Power Supply Rejection Ratio(PSRR) of 79dB in the low frequency. The results of simulation show that the design improve the performance of the bandgap reference voltage source effectively.

In this paper, a high-precision temperature sensor designed by a standard 0.18μm CMOS process with 3.3-V power supply is presented. The CMOS temperature sensor mainly consists of a bandgap reference (BGR) circuit and a SAR ADC circuit. In the BGR circuit, not only the traditional first-order compensation technique is adopted, but also a high-order curvature correction technique is used to obtain two accurate reference voltages, which are adopted as reference voltages for the SAR ADC, and a twice emitter-base voltage of BJT is used as a temperature sensing voltage for the SAR ADC. Simulation results show that temperature coefficients of two reference voltages are as low as 1.16 ppm/°C and 3.66 ppm/°C over a temperature range of 165°C (-40°C to 125°C), PSRRs are up to −100 dB at low frequency. The CMOS temperature sensor achieves 0.1°C temperature resolution, and ±0.35°C absolute accuracy.

A novel band-gap reference circuit is presented in order to reduce the offset voltage and power consumption. By using the op-amp input voltage as part of the reference voltage source, the gain and power supply rejection ratio of the op-amp is increased. The working principle of the Band-gap reference circuit is analyzed, and it is pointed out that the temperature coefficient becomes smaller through using the temperature compensation. The simulation results based on xiyue 0.3um bipolar process show that the circuit has low power dissipation and good temperature characteristic, the power supply rejection ratio is up to 92dB. The correctness of the theoretical analysis is verified by simulation results.

This paper proposes a novel curvature‐correction technique insensitive to process variations, which can be used in not only the bandgap reference (BGR) circuit but also the Zener reference circuit. By using two BJT transistors to form a differential pair structure, the current difference between the differential pair generates a compensation current, which compensates for the non‐linearity in the reference voltage. Unlike the classic curvature‐correction technique which can only be used in the BGR circuit, this novel technique can be used in the Zener reference circuit as well. What is more, the proposed curvature‐correction technique is insensitive to process variations, which greatly increases the reliability of commercial products. Finally, simulation results verify the validity of the proposed technique.

The accelerated aging stress test is essential for assessing the reliability and quality of band gap reference (BGR) circuits, which are crucial for maintaining consistent voltage references in ICs. In this study, we present accelerated aging analysis of a classic BGR design as an case study. A BGR circuit, validated on a Quality and Reliability On-Chip (QROC) platform, demonstrated temperature coefficient of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.12 \text{ mV} /{}^{\circ} \mathrm{C}$</tex> across 25° C to 100° C, ensuring minimal drift with temperature fluctuations. The output reference voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(V_{{ref}}) 646$</tex> mV was measured over a supply voltage range of 0.8V to 1.4V, with a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\pm 7.5 \text{ppm} / \mathrm{V}$</tex>. The circuit's robustness was further confirmed by observing only a 1% change in <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{{ref}}$</tex> after a million-second stress test at varying temperatures and a stress voltage 1.4V. This result, showing less than 6.5% deviation from post-layout simulations, underscores the BGR's resilience and precision, highlighting the importance of such stress testing in predicting IC performance and longevity.

A high precision band-gap reference (BGR) with piecewise-linear compensation is designed in this paper. A low voltage Brokaw BGR architecture is employed to provide low output voltage. A high gain, low power supply rejection ratio (PSRR) operational amplifier is designed to improve the PSRR of the band-gap reference. In order to achieve temperature stability significantly lower than the traditional band-gap reference, a circuit which produces a current with positive temperature coefficient (TC) at high temperatures and 0 current at lower temperatures is designed. The whole BGR circuits are simulated by Spectre based on chartered 0.18μm 1P5M 1.8V CMOS technology. It's clear from simulation result that the TC of the output reference voltage approaches 2.61ppm/K over the military temperature range, the PSRR reaches 107.2dB at low frequency (f=0.1HZ), the whole BGR dissipates 0.4mW. In addition, the output reference voltage changes only 8.6μV when the power supply changes from 1.5V to 2.1V, that is to say, the power regulation ratio is 0.014mV/V.

This paper presents a curvature-compensated bandgap reference (BGR) circuit implemented in 0.35 /spl mu/m CMOS technology. The circuit delivers an output voltage of 1.09 V and achieves a temperature coefficient of 3.1 ppm//spl deg/C over [-20/spl deg/C, 100/spl deg/C] after trimming, a power supply rejection ratio of -80 dB at 1 KHz and an output noise level of 1.43 /spl mu/V/sqrt(Hz) at 1 KHz. The BGR circuit consumes a current of 37 /spl mu/A and the power supply ranges from 1.5 V to 3.3 V.

CMOS image sensor is a rapidly developing image sensor product in the past decade. Relying on the advantages of process compatibility with standard CMOS process, CMOS image sensor integrates analog photoelectric photosensitive circuit and digital signal processing circuit to become a small and powerful system on chip. This article mainly studies the explosive growth of image sensors in smart government technology and economic scale. The main purpose of this article is to study the technical application of image sensors, reduce the administrative cost of social governance, improve the level of government governance, benefit the public, and realize the requirements of smart government affairs and rapid economic development of the city. This study tested the static performance of the analog-to-digital conversion circuit by inputting a limited number of sampling points, and its integral nonlinearity and differential nonlinearity were both less than 1LSB. The bandgap reference circuit provides a reference level for the entire system. It uses two PNP-type bipolar transistors parasitic in the CMOS process to achieve a temperature and voltage-independent bandgap reference voltage through the feedback of the operational amplifier. It is ideal for use In the case of resistance simulation, its accuracy reaches 16.6ppm. The scanning method of the pixel array uses multi-sampling technology to increase the dynamic range of the sensor by 2N times. The correlated sub-sampling technology eliminates the fixed pattern noise between pixel units. The use of pipelined analog-to-digital converters can achieve good resolution, speed and area compromise.Through the realization and simulation of transistor-level circuits, the performance of each part of the system meets the requirements of design and application.

A precise high-order segmented curvature-compensation bandgap reference (BGR) with dynamic element matching (DEM) offset cancellation has been developed. The proposed segmented curvature-compensation scheme with a resistive trimming network is used to reduce the errors caused by the nonlinear dependence of the bipolar transistor base-emitter voltage (VBE) on temperature. To decrease the std dev (σ) of the reference voltage (VREF), DEM technology is applied in the core BGR to alleviate the current branch mismatch, as well as the current mirror mismatch in the error amplifier. The proposed BGR circuit is designed on a 0.18 μm BCD process with an active area of 300×375μm and 61.5 μA@5 V current consumption in the bandgap core circuit. The post-simulation results show that the proposed BGR achieves a temperature coefficient (TC) of 0.81–1.46 ppm/°C from −40 °C to 125 °C and a 0.045% σ/μ variation on a 3.2768 V VREF.

A high-order curvature-compensated CMOS bandgap reference (BGR) topology with a low temperature coefficient (TC) over a wide temperature range and a high power supply reject ratio (PSRR) is presented. High-order correction is realized by incorporating a nonlinear current INL, which is generated by ∆VGS across resistor into current generated by a conventional first-order current-mode BGR circuit. In order to achieve a high PSRR over a broad frequency range, a voltage pre-regulating technique is applied. The circuit was implemented in CSMC 0.5 μm 600 V BCD process. The experimental results indicate that the proposed topology achieves TC of 0.19 ppm/°C over the temperature range of 165 °C (−40 to 125 °C), PSRR of −123 dB @ DC and −56 dB @ 100 kHz. In addition, it achieves a line regulation performance of 0.017%/V in the supply range of 2.8–20 V.

This article presents a low-power bandgap reference (BGR) featuring high power supply rejection ratio (PSRR) and fast start-up capability, operating across a wide supply voltage range of 1.3–5 V. A novel prebiased pulse current injection technique is proposed in the start-up circuit, achieving a 1% settling time of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$50~\mu $</tex-math> </inline-formula>s and a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$25\times $</tex-math> </inline-formula> speed gain during start-up. To enhance supply noise immunity, the proposed BGR employs a preregulated (PR)-based amplifier that effectively decouples the reference voltage from supply voltage fluctuations. Fabricated in a 0.18-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula>m BCD process, the proposed reference occupies an active area of 0.0394 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. Under a 5 V supply, the circuit generates a 1.2 V reference voltage while consuming only 48 nA quiescent current. Operating down to a minimum supply voltage of 1.3 V, it maintains a low power consumption of 57.2 nW at room temperature. The reference exhibits an average temperature coefficient (TC) of 5.95 ppm/°C across a wide temperature range (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$- 40~^{\circ }$</tex-math> </inline-formula>C to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$125~^{\circ }$</tex-math> </inline-formula>C) and achieves an outstanding line sensitivity (LS) of 0.00308%/V over the 1.3–5 V supply range. Furthermore, the measured PSRR reaches −85 dB at 100 Hz.

A BiCMOS current source reference network which eliminates the impact of DC power supply voltage drops on the operation of ECL (emitter coupled logic) circuits is described. This is essential for implementing ECL design techniques in ULSI BiCMOS circuits. Using the current source network, reference voltages are generated locally, so that the ECL voltage references are correctly referenced to the local power supply potentials. A power-supply-insensitive bandgap reference generator is used to generate precision on-chip voltage references and current sources. The bandgap reference circuit uses both MOS and bipolar transistors and is much simpler than a similar design using bipolar-only circuitry. The micrograph of the test chip containing the bandgap circuit nd BiCMOS op amp analog drivers is shown. The drivers are designed for multiple-reference-level regeneration. The test chip has been fabricated using a 0.8- mu m BiCMOS process. The typical characteristics of the bandgap circuit and the analog driver are shown. >

Due to the offset voltage which introduced by the mismatch and the channel-length modulation, the bandgap reference circuit in CMOS technologies is usually nonlinearly, and the design of bandgap references with high precise is a challenging circuit design problem. In this paper, we propose a method of optimizing the parameters of the components to compensate the non-linearity offset voltage using the backpropagation based neural networks. The method for training the network is investigated based on the coefficients of the input and output voltage of the circuit which make the training computationally efficient. The experimental results show that with the network structure approximation, the non-linearity of offset voltage can be reduced markedly, and the accuracy of bandgap reference is improved 10 times.

Bandgap reference (BGR) circuits are widely used due to their stable output voltage over process, supply voltage and temperature variations. Reference voltage stability is critical for data-acquisition applications and lower supply voltages can reduce the power of mixed-signal systems. However BGR for analog circuits is one of the bottlenecks for sub-1V supply operation because BGR supply voltage is limited by V EB +V DS [1]. V EB refers to the emitter-base voltage of a pnp transistor which is limited to ~0.6 to 0.7V due to silicon junction cut-in voltage, while V DS is the drain-source saturation voltage of a current-mirror. The BGR temperature dependence is decided by the weighted sum of proportional-to-absolute-temperature(PTAT) and complementary-to-absolute-temperature (CTAT) terms. An alternative PTAT generator can be implemented by dV GS (gate-to-source voltage difference) of a MOS pair in subthreshold [2]. The CTAT generator can be implemented by special devices or using the gate-source voltage V GS of subthreshold MOSFETs. Although the V GS of a subthreshold MOSFET is smaller than emitter-base voltage of a pnp transistor, the MOSFET model inaccuracy in the subthreshold region and high process-dependent characteristic of MOSFET gate-source voltage induces high variation for voltage reference circuits.