A Highly Reliable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source

Physically unclonable functions (PUFs) have been explored as lightweight hardware primitives for the purpose of realizing robust security via strong authentication or secure key/ID generation. PUF harness manufacturing process variations for the purpose of generating binary keys or binary functions. An ideal strong PUF is a binary function that maps an m-bit input challenge to an uniquen-bit output response, making it attractive for authentication applications. Unfortunately, real strong PUF implementations suffer from reliability issues where the same challenge may produce different responses in the presence of noise. To overcome this problem, strong PUF leverages the availability of exponential number of challenge-response pairs (CRPs). A successful authentication event requires acquiring multiple CRPs and applying a threshold. In contrast, weak PUFs produce limited keys and are required to be highly reliable. Multiple techniques have been developed to achieve the necessary reliability. An additional prerequisite for strong PUFs is resilience against model-building attacks (cloning) by an adversary, who has observed a few CRPs, to prevent successful prediction of future CRPs. In this work, we first illustrate a strong PUF design that re-purposes a weightless neural network (WNN). Second, we showcase the robustness of WNN-based strong PUFs with respect to machine learning attacks, while providing desirable uniqueness and reliability metrics. Finally, we employ an initial entropy source of highly reliable weak PUF bits mapped to weightless neural networks (WNNs) for the purpose of creating a near-ideal strong PUF in terms of reliability. Our results show that it is possible to create highly reliable WNN–based strong PUFs with < 65 % ML accuracy by using as few as 32 initial reliable weak PUF bits.

The Internet of things (IoT) ecosystem has grown exponentially with the convergence of various technologies such as deep learning, sensor systems, and advances in computing platforms. With such a highly pervasive nature of “smart” devices, the nature of data being collected and processed can be increasingly private and require safeguards to ensure the data’s integrity and security. Physically unclonable functions (PUFs) have emerged as a lightweight, viable security protocol in the Internet of Things (IoT) framework. Malicious modeling of PUF architectures has proven to be difficult due to the inherently stochastic nature of PUF architectures. In this work, we show that knowledge of the underlying PUF structure is unnecessary to clone a PUF. We tackle the problem of cloning PUF-based edge nodes in different settings such as unencrypted, encrypted, and obfuscated challenges in an IoT framework. We present a novel non-invasive, architecture-independent, machine learning attack for robust PUF designs and can handle encryption and obfuscation-based security measures on the transmitted challenge response pairs (CRPs). We show that the proposed framework can successfully clone different PUF architectures, including those encrypted using two (2) different encryption protocols in DES and AES and with varying degrees of obfuscation. We also show that the proposed approach outperforms a two-stage brute force attack model. Finally, we offer a machine learning-based countermeasure, a discriminator, which can distinguish cloned PUF devices and authentic PUFs with an average accuracy of 96%. The proposed discriminator can be used for rapidly authenticating millions of IoT nodes remotely from the cloud server.

Communication security is essential for the proper functioning of the Internet of Things. Traditional approaches that rely on cryptographic keys are vulnerable to side-channel attacks. Physical Unclonable Functions (PUFs), leveraging unavoidable and irreproducible variations of integrated circuits to produce responses unique for individual PUF devices, are emerging as promising candidates as security primitives to provide keyless solutions. Before a PUF can be adopted for real applications, the PUF must be thoroughly examined to understand its various properties for its application feasibility. In this paper, we study XOR PUFs for broad ranges of values for circuit architecture parameters. XOR PUFs have been extensively studied, and have been shown to be unable to withstand machine learning attacks for 64-bit XOR PUFs with less than ten component PUFs. Attack methods employed in existing studies need a large number of challenge-response pairs (CRPs), which are obtainable only if the PUF has an open access interface. When PUF-embedded devices equipped with mutual authentication or response obfuscating techniques, it is difficult for attackers to accumulate large numbers of CRPs. With only a small number of accumulated CRPs available to attackers, small size PUFs, like XOR PUFs with a small number of component PUFs and stages, may become resistant to machine learning attacks. Since smaller sizes mean less resource-demanding, it is worthwhile to examine such PUFs which have usually been considered unsafe against attacks. Such are thoughts that have been motivating us in this paper to explore the PUF performances for a wide range of values of the PUF architecture parameters.

Modern embedded electronic devices are gradually becoming an essential part of everyday lives, proving indispensable for daily activities. The growth of the Internet of things (IoT) technology fuels this phenomenon. IoT devices are found everywhere around us – smartphones, smartwatches, home automation, autonomous cars, and medical implants for human bodies. These devices find widespread use in medical imaging, video surveillance as embedded vision, cloud computing platforms, and military applications. Ensuring the reliability and safety of these devices is of prime importance, since these devices store sensitive data. A wide range of such embedded devices is a common target for intellectual property (IP) theft and reverse-engineering attacks by hackers to access confidential information and counterfeit integrated circuits. Physically unclonable functions (PUFs) are innovative hardware defense techniques that promise a fundamental change in our approach to many security problems. PUFs possess desirable properties like low cost, simple architectures, a light weight, versatility, and the valuable advantage of unclonability. This unclonable property is a consequence of intrinsic random variations at the micro- and nanoscale levels in the manufacturing processes and cannot be controlled or removed. This characteristic also serves as a unique fingerprint for the integrated circuit chips, similar to humans. The widespread usage of PUF techniques in security applications makes it imperative for hardware designers to appreciate its working and understand its uses in practice fully. This chapter aims to address these and other topics by presenting a detailed introduction of the concepts, evaluation parameters, and various ramifications of physically unclonable functions. PUF techniques also provide an economical alternative to ciphers and hash functions for secure cryptographic protocols. It is also necessary to provide security of IoT devices, have economic viability, and fit well with embedded devices’ heterogeneous nature. PUF circuits receive challenges as a sequence of bits and generate matching responses called a challenge-response pair, which can be thought of as a secret key or unique fingerprint. It also obviates the need for storing the keys in nonvolatile memories with dedicated protection, which is a costly affair. In this chapter, different PUFs, including optical PUF, delay-based PUFs, weak and strong PUFs, etc., the maturity of this technology, and their various applications are investigated. This chapter also emphasizes critical challenges toward PUF utilization in IoT and related fields and significant future development areas like critical public infrastructure, reconfigurability, and bit-specific reliability. The unique IoT domain protection criteria and how PUFs can be used to fulfill them are also examined. The chapter’s emphasis is on proven and well-understood strategies involving their benefits and shortcomings.

The use of physically unclonable functions (PUFs) as a new cryptographic technique is gaining attention. Challenge-response authentication and key generation (key storage) are well known as major applications using PUFs. When PUFs are applied to these applications, min-entropy estimation is essential. The min-entropy is a measure of the lower bound of the unpredictability of PUF responses. Many studies have estimated the min-entropy of PUFs, and several of these studies dealt with PUFs with independent and identically distributed (IID) PUF responses. Few studies have focused on non-IID PUFs. One reason is that some causes of entropy loss are complicatedly intertwined, and the entropy estimation of non-IID PUFs is hard. Thus, it is first necessary to break down the intertwined causes to estimate min-entropy. In this paper, we present typical causes of entropy loss during PUF implementation and propose a cause analysis method using the Inter-Hamming distance (HD), which is one of major performance metrics of PUFs. And the proposed method was applied to prototyped PUFs designed with a 180-nm CMOS process. We demonstrate that the causes of entropy loss on each PUF can be broken down according to the analysis results.

The introduction of Physical Unclonable Functions (PUFs) has been originally motivated by their ability to resist physical attacks, particularly in anti-counterfeiting scenarios. In these one-way functions, machine learning, cryptanalysis, and side-channel attacks are common attack vectors threatening the promised PUF's property of unclonability. These attacks often emulate a PUF by employing a large number of Challenge-Response Pairs (CRPs). Some solutions to defeat such attacks are based on a protocol, where a model of the underlying PUF primitives should be extracted during the enrollment phase. In this article, we introduce a novel physical cloning approach applicable to FPGA-based implementations, which allows extracting the PUF's unique physical characteristics with a few number of Challenge-Response Pairs (CRPs), that increases only linearly for a higher number of PUF components. Indeed, our proposed approach significantly accelerates the enrollment phase and makes complex enrollment protocols feasible. Our core idea relies on an on-chip delay sensor, which can be realized by ordinary FPGA components, measuring the unique characteristic of the PUF elements. We demonstrate the feasibility of our introduced technique by practical experiments on different FPGA platforms, cloning a couple of (complex) PUF constructions, i.e., XOR APUF, iPUF, composed of delay-based Arbiter PUFs.

A Physical Unclonable Function (PUF) is often used to uniquely identify an integrated circuit by extracting its internal random differences using so-called Challenge Response Pairs (CRPs). As CRPs include unique information about the underlying hardware variations, PUF design is a promising approach to provide authentication and IP-protection capabilities. In this paper, an XOR-gate-based configurable Ring Oscillator (RO) PUF (denoted as XCRO PUF) is presented. This XCRO PUF can generate more CRPs compared with state-of-the-art PUF designs by using the same number of configurable logic blocks (CLBs) in an FPGA implementation. This design is implemented in the Xilinx Spartan-6 XC6SLX9 FPGAs with fixed locations for the XCROs (placed within a ring to improve its uniqueness). The XCRO PUF shows better uniqueness and reliability than other PUF designs. Moreover, a XCRO PUF consumes only 12.5% of the hardware resources to generate a 1-bit response compared with other CRO PUFs implemented in FPGA.

Physical Unclonable Functions (PUF) are an emerging hardware security primitives proposed by various researchers in last one decade. PUFs are useful security architectures used for identification, authentication and cryptographic key generation. Many PUF topologies are proposed in the past targeting both ASIC and FPGA. It is nearly impossible to get two PUF circuits with same characteristics for the same design. PUFs make use of random process variation occurring during manufacturing of IC which is uncontrollable. The most versatile PUF is ring oscillator (RO) PUF, in which the frequencies of ring oscillators are compared to produce the PUF response. The conventional approach consumes large number of ring oscillators and requires all RO's to be mutually symmetric. In this paper, we have proposed a RO-PUF for FPGA devices, which is capable of generating multiple output bits from each ring oscillator with better security metrics in comparison with PUF designed with similar technique. The PUF is implemented on Xilinx Spartan 3E FPGA boards and the challenge-response pairs (CRP) are verified for statistical properties.

A Physical Unclonable Function (PUF) is a promising security primitive for low cost security solutions. It is especially attractive for resource constrained platforms such as internet-of-things (IoT) devices. A novel Tristate Static Random Access Memory (TSRAM) PUF design consisting of two cross-coupled tristate inverter arrays is proposed in this paper. This new PUF structure is able to reconfigure the cross-coupled inverters so that it can produce effective challenge-response pairs (CRPs) without using any additional auxiliary processing, which is not available in previous memory based PUFs. The functionality and performance of the proposed TSRAM PUF is validated by both simulation with UMC 65nm technology and practical experimentation on a Xilinx Virtex-II FPGA. The proposed TSRAM PUF demonstrates good uniqueness and reliability and it uses the smallest number of gates to produce one response bit compared with previous works.

In the deployment of millions of edge devices connected via Internet of Things (loT), each of those devices are exposed as access points for security attacks. As a primitive solution to breaches, physical unclonable functions (PUF) are considered as one of the most cost/energy-efficient approaches providing hardware-oriented randomness, uniqueness, and reliability. PUF can be fundamentally classified into strong and weak PUFs. Strong PUFs can generate a large number of challenge-response pairs (CRPs) according to the given secret. However, due to the correlation between CRPs, it is vulnerable to attacks through the heuristic learning. On the other hand, weak PUFs typically produce a relatively small number of CRPs. Therefore, not only ideal uniqueness and stable response against voltage/temperature variations are important, but also efficient PUF cell area per bit ($\left.\mathrm{F}^{2} / \mathrm{bit}\right)$ is a critical metric for weak PUFs to produce a large number of CRPs with high density.

The designs of Physically Unclonable Functions (PUFs) described in this paper are based on Resistive RAMs incorporating ternary states with the objective to reduce false negative authentications (FNA) with low Challenge-Response-Pair (CRP) error rates. Unlike other error correction method, the method is not increasing false positive authentications (FPA). The ternary states, the Xs, allow the blanking of all cells that are not characterized as consistently capable to generate stable and easy to read 1s or 0s PUF challenges. Experimental data extracted from Cu/TaOx/Pt Resistive RAM samples confirms that such a method can generate CRPs having error rates below 8 ppm useable for secure hardware authentication. Random Number Generators (RNG) can also be enhanced by the same ternary architecture.

Physically unclonable functions (PUFs) have drawn attention as one of the key security primitives for IoT devices since they can provide unique, random, stable, and unclonable hardware fingerprints, ie. keys, for secure authentication. Numerous PUF designs have been evolved to provide stable keys at a lower cost, ie. with small area. Early SRAM-based PUFs [1, 2] had large area $(\gt9,000{\mathrm {F^{2}/bit}})$ and was unstable with a native BER of 8.3*. Various stabilization techniques were proposed such as temporal majority voting (TMV), burn-in, and dark bit masking, at the cost of large additional peripheral circuits and significant loss of challenge-response-pairs (CRPs). But resulting BER was still very high ($\sim$ 1*) even with 8.6x BER improvement. An inverting logic gate cell-based PUF with high reliability [3] and synthesizable PUF [4] were also proposed but the large area (5,057F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /bit,2,686F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /bit) limited cost efficiency. A 2-T amplifer-based PUF achieved 553-782F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /bit area [5, 6] but the initial version had a high BER due to the lack of a stabilization method [5]. Therefore, in the following work [6], a stabilization method was subsequently proposed and BER could be significantly improved. A leakage-based PUF with a lossless stabilization method called ‘remapping’ was proposed in [7], which allowed stabilization without sacrificing CRPs as required in [1–3, 6]. To further improve cost efficiency, a PUF with a differential NAND structure [8] was proposed with an extremely small area of $20{\mathrm {F^{2}/bit}}$. However, there was no means of stabilization applicable, other than TMV, making it unstable and susceptible to voltage or temperature (V/T) variations. Therefore, in this paper, a current-integrated differential NAND-structured PUF (CI NAND-PUF) is proposed, where stabilization methods other than TMV is made applicable. By applying trimming and remapping, up to 12.8x stability improvement is achieved with extremely cost-efficient PUF with 20F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /bit area, while also significantly reducing peripheral circuit overhead on [8].

The silicon primitives known as Physically Unclonable Functions (PUFs) are used for various security purposes including key generation, device authentication, etc. Due to the imperfections in manufacturing process, PUFs produce their unique outputs (responses) for given input signals (challenges) fed to identical circuitry designs. Although PUFs are deployed to preserve security and are assumed to be unclonable, their functionality may still be compromised by modeling attacks. However, such attacks only target one single PUF aiming at reversing its behavior (based on a subset of its challenge-response pairs), and are not useful for attacking other PUFs. Moreover a subset of the target PUF's response has to be known by the attacker. This paper moves one step forward and investigates the possibility of Cross-PUF attacks in which a particular PUF's power fingerprints can be used to break another PUF's security. In these Cross-PUF attacks, the attacker has at his disposal a reference PUF, and uses its power side-channel to train a machine learning model which can be deployed to attack other identical PUFs. The experimental results show the high success of the proposed attacks even in presence of noise and temperature differences between the target PUF and the one used to train the model. We target arbiter-PUFs but we deduce that the findings extend to all its derivatives, e.g., XOR-PUFs and Feed-Forward-PUFs.

CRPUF: A modeling-resistant delay PUF based on cylindrical reconvergence

Physically unclonable functions (PUFs) have been widely proposed as hardware primitives for device identification and cryptographic key generation. While strong PUFs provide an exponential number of challenge–response pairs (CRPs) for device authentication, most are vulnerable to machine-learning (ML)-based modeling attacks. Regarding the inherent hard learning problem, adversarial-based PUFs pseudo-randomly switch between several predefined internal states to poison the ML algorithms. However, existing adversarial-based PUFs sacrifice reliability or security against ML attacks. Furthermore, most works only evaluated the ML resistance by empirical experiments, which provides limited evidence for ML resistance. This work explored a novel adversarial-based PUF, Configurable Poisoning PUF (CP PUF), that simultaneously maintains reliability and protects the internal state by a reliability trapdoor. We then connect the proposed CP PUF with the learning parity with noise (LPN) problem to provide a theoretical security guarantee. Experiments show that the reliability of our proposed CP PUF keeps at least 88.9% and outperforms the existing adversarial-based PUFs under different levels of noisy environments. Moreover, the proposed CP PUF achieved a 50.16% accuracy under empirical ML attacks, a near-optimal performance.