A less configuration memory reconfigurable logic device with error detect and correct circuit

We have investigated the effects produced by exposing a field programmable gate array (FPGA) based on static RAM to an ion beam. Tested devices have been taken from FLEX10K family manufactured by Altera Corporation. These parts are commercial graded and not qualified for application in radioactive environments. A design based on mixed plain and triple-modular-redundant (TMR) shift registers (SR's) has been implemented in the FPGA under test. No single event upset (SEU) was detected in the shift registers. The predominant effect of irradiation with heavy ions was the single event functional interrupt (SEFI). SEFI's have been induced from SEU's in the configuration memory. No destructive latch-up has been observed. During irradiation, supply current has been observed to increase almost linearly with ion fluence, probably due to progressive SEU-induced driver contentions. The configuration memory cross section has been calculated and we have found the saturation level of 2.5/spl middot/10/sup -8/ cm/sup 2/ /bit reached with LET>40 MeV/spl middot/cm/sup 2//mg.

In this chapter we present an experimental methodology to study the Single Event Effects (SEE) in Field Programmable Gate Arrays (FPGAs) by using heavy ion beam irradiation. We present also some results obtained at a Van Der Graaff Tandem accelerator facility. Test methodology is based on the implementation of four Shift-Registers (SRs), two of them by using Triple-Modular-Redundant (TMR) technique. The SRs functionality is continuously checked during irradiation and errors are immediately and automatically logged and timestamped by the control system. Irradiation experiments have been performed on commercial FPGAs manufactured by Altera. These devices are based on static RAM configuration memory. No Single Event Upset (SEU) was detected in the shift registers upon irradiation. Instead, the predominant effect of heavy ion irradiation was the Single Event Functional Interrupt (SEFI). SEFIs are likely induced by SEUs in the configuration memory. No destructive latch-up has been observed. During irradiation, supply current has been observed to increase almost linearly with ion fluence, probably due to progressive SEU-induced driver contentions. The configuration memory cross section has been calculated.Key wordsFPGAirradiationCOTSSEUSEFI

Reconfigurable computing using field programmable gate arrays (FPGAs) offer significant performance improvements over traditional space based processing solutions. The application of commercial-off-the-shelf (COTS) FPGA processing components requires radiation-effect detection and mitigation strategy to compensate for the FPGAs' susceptibility to single event upsets (SEUs) and single event functional interrupts (SEFIs). A reconfigurable computing architecture that uses external triple modular redundancy (TMR) via a radiation-hardened ASIC provides the most robust approach to SEU and SEFI detection and mitigation. Honeywell has designed a TMR Voter ASIC with an integrated FPGA configuration manager that can automatically reconfigure an upset FPGA upon TMR error detection. The automatic configuration manager also has features to support resynchronizing the upset FPGA with the remaining two FPGAs operating in a self checking pair (SCP) mode. Automating and minimizing reconfiguration times and re synchronization times enables high performance FPGA-based processors to provide high system availability with minimal software/system controller intervention.

Triple modular redundancy (TMR) is a single-event upset (SEU)-mitigation technique that uses three circuit copies to mask a failure in any one copy. It improves the soft error reliability of designs implemented on SRAM-based field-programmable gate arrays (FPGAs) by masking the effects of upsets in the configuration memory. Although TMR is most effective when applied to an entire FPGA design, a reduction in the sensitive cross section of an FPGA design can be obtained by applying TMR selectively. This article explores several approaches for selecting components to triplicate. The benefit is a reduction in the neutron cross section for any output error as a percentage compared to that of a non-triplicated design. The cost is the percentage of components triplicated. The goal is to maximize the benefit-cost ratio. Twenty-five different selections are tested on a benchmark design. Some selections increase the cross section; others decrease the cross section significantly.

Two field-programmable gate array (FPGA) designs are tested for dynamic single event upset (SEU) sensitivity on two different 28-nm static random access memory-based FPGAs—an Intel Stratix V and a Xilinx Kintex 7 FPGA. These designs were tested in both a conventional unmitigated version and a version to tolerate SEUs with feedback triple modular redundancy (TMR). The unmitigated design sensitivity and the low-level device sensitivity were found to be similar between the devices through neutron radiation testing. Results also show that feedback TMR and configuration scrubbing benefit both designs on both FPGAs. While TMR is helpful, the benefit of TMR depends on the design structure and the device architecture. TMR and scrubbing reduced dynamic SEU sensitivity by a factor of 4– $54\times $ .

SRAM-based FPGA designs are extremely susceptible to single event upset (SEUs). Since the configuration memory defines which is the circuit an SRAM-based field programmable gate array (FPGA) implements, any change induced by SEUs in the configuration memory may modify drastically the implemented circuit. When such devices are used in safety-critical applications, fault tolerant techniques are needed able to mitigate the effects of SEUs in FPGA's configuration memory. In this paper we present a reliability-oriented place and route algorithm that is able to mitigate the effects of the considered upsets.

The mitigation of single event upset (SEU) in SRAM based Field Programmable Gate Array (FPGA) is increasingly important as it is widely used in radiation environments such as space. As D flip-flop (DFF) and memory (including Block RAM and Configuration RAM) are the key elements in FPGAs, it is crucial to develop radiation hardening techniques for enhanced reliability of the DFF and memory. A novel hardened memory design for FPGA is proposed with multi-bit upset (MBU) protection. We further developed two prototype FPGA chips, one with and the other without SEU hardening for comparison. The FPGA chips are fabricated in a standard 0.13μm CMOS process and have a volume of 3 million equivalent logic gates. In contrast to the base FPGA, the SEU cross section of the memory in the hardened FPGA is at least three orders of magnitude lower. Also, no SEU upsets are observed in the DFF of the hardened FPGA.

Neutron radiation environment in near space is analyzed by Space Radiation 7.0 toolkit. It is found that neutron flux decreases by several orders as altitude increases, low-energy neutron flux increases sharply at solar maximum condition, neutron flux increases constantly as latitude ascends. The inner reasons are further investigated. Based on the results, a prediction technique of atmospheric-neutron induced Real-Time Soft Error Rate (RTSER) using Monte-Carlo method is proposed. Taking Field Programmable Gate Array (FPGA), critical Integrated Circuit (IC) used in avionics system, as an example, the RTSERs of Single Event Upset (SEU) sensitive modules (including Configurable Memory (CM), Block Random Access Memory (BRAM) and user Flip-Flops (FF)) and Single Event Functional Interrupt (SEFI) sensitive modules (including Power-On-Reset (POR), SelectMAP <i>etc</i>.) are predicted. The results show that SEUs in CM accounted for 77% of the total SEU rate in the FPGA. Both POR and SelectMAP SEFIs accounted for 36% of the total SEFI rate respectively. According to the failure levels of flight system in RTCA DO-254, the FPGA can not be employed in key positions of avionics.

The mitigation of single-event upsets (SEUs) in field-programmable gate arrays (FPGAs) is an increasingly important subject as FPGAs are used in radiation environments such as space. Triple modular redundancy (TMR) is the most frequently used SEU mitigation technique but is very expensive in terms of area and power costs. These costs can be reduced by sacrificing some reliability and applying TMR to only part of the FPGA design. Our partial TMR method focuses on the most critical sections of the design and increases reliability by applying TMR to continuous sections of the circuit. We introduce an automated software tool that uses the Partial TMR method to apply TMR incrementally at a very fine level until the available resources are utilized. Thus the tool aims to gives the maximum reliability gain for the specified area cost.

Static random-access-memory-based field-programmable gate array devices are an attractive option for onboard data processing in space systems due to higher computational capabilities and a lower power envelope than traditional processing devices. However, field-programmable gate arrays present unique reliability verification challenges because single-event upsets can trigger both data errors and configuration memory errors, which may cause deviations from the expected system functionality. To evaluate system reliability, traditional fault-injection testing uses numerous test vectors to observe the effects induced by a change of a single configuration memory bit at a time. This single-bit fault-injection methodology provides high fault coverage and testing repeatability, but it requires a long fault-injection time due to the large number of test vectors required to verify the entire design’s functionality. Long injection times are further exacerbated as configuration memory size and design complexity increase. To shorten injection time, a Simple, Portable Fault Injector platform is proposed for field-programmable gate arrays used in tandem with a novel multibit fault-injection methodology that modifies multiple configuration memory bits, referred to as a batch, during each test. The proposed methodology is optimized to efficiently detect the faulty bits within a batch, adaptively select the optimal batch size, and optimize the fault-injection sequence based on the design’s placement. Using relevant case studies, Simple, Portable Fault Injector for field-programmable gate arrays augmented with multibit fault-injection methodology reveals up to 50 times the speedup in fault-injection time.

Convolutional neural networks (CNNs) are quickly becoming an attractive solution for autonomous vehicles, military weapons, and space exploration. Thanks to their reconfiguration ability, design flexibility, and low power consumption, field-programmable gate arrays (FPGAs) have become a promising candidate for CNN accelerators. However, FPGAs have been proven to be susceptible to radiation-induced single-event upsets (SEUs). One goal of this article is to analyze the impact of quantization on the reliability of CNNs in FPGAs. Therefore, we performed quantization on ZynqNet without affecting its classification accuracy. Meanwhile, we implemented the triple modular redundancy (TMR) version of ZynqNet and we also evaluated the effects of SEUs on these CNNs through both fault injections and neutron exposures. Fault injection results show that TMRed ZynqNet reduces the soft error rate (SER) by 33.59% with a circuit area increase of 111.92% when compared with the standard ZynqNet. The experimental results demonstrate that the quantized ZynqNet reduces the SER by 71.36% with a circuit area reduction of 44.76% when compared with the standard ZynqNet. These results confirm that quantization does contribute to SER reduction of the neural networks. In addition, the operating system on the processing system (PS) side was also found to be highly sensitive to SEUs, and, thus, mitigation techniques should be applied.

Objectives. Programmable logic integrated circuits of the field programmable gate array (FPGA) type based on static configuration memory are widely used in the electronics of onboard spacecraft systems. Under the influence of space radiation, errors may occur in the FPGA configuration memory. The main methods of protection against such errors involve various options for reservation triggers, as well as the use of error-correcting codes in special error detection and correction circuits. The purpose of the present work is to determine which error-correcting codes are best suited to the implementation of internal scrubbing of the FPGA configuration memory taking redundancy into account.Methods. The paper analyses various methods for scrubbing FPGA configuration memory, which are used to correct errors caused by the action of space radiation. It is proposed to increase the efficiency of internal scrubbing of the FPGA configuration memory using codes that correct both single- and double-adjacent SEC-DED-DAEC errors. In this case, the need to perform external scrubbing of the configuration memory is reduced by overwriting it with a reference configuration from non-volatile radiation-resistant memory; in this way, FPGA downtime caused by the external scrubbing procedure is reduced. Due to the known SEC-DED-DAEC codes having a non-zero probability of erroneous detection and subsequent erroneous correction of a double non-adjacent error, as well as various redundancy and implementation complexities, a study was made of the most efficient code for internal scrubbing.Results. The results showed that the Datta, Neale and Hoyoon–Yongsurk codes are optimal from the indicated positions. Recommendations are given for selecting a specific code depending on the specific requirements for a particular planned space mission.Conclusions. The study confirms the effectiveness of protecting the memory of programmable logic by using two-error-correcting codes.

In harsh environments, such as space, radiation, and charged particles cause single-event effects (SEEs), faults occurring randomly on any electronic component. These must be mitigated to ensure device functionality. Modern mitigation methods, such as triple modular redundancy (TMR), are very effective against single-event transients (SETs) but incur a minimum of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\times $ </tex-math></inline-formula> cost in the area. Single-event upsets (SEUs) affect sequential elements and are regularly repaired using memory scrubbing. Scrubbing is a slow serial process going through every memory word, looking for errors to repair. Scrubbing involves a nonnegligible amount of time before an error is detected, during which other events can occur and compromise the system. Field-programmable gate arrays (FPGAs) rely heavily on sequential elements to store their configuration; thus, FPGA’s SEU detection time is critical to ensuring design sustainability in harsh conditions. In this article, we propose an alternative mitigation method based on sensor integration and FPGA architecture modification, called smart-redundancy with in-memory error correction code checking (SRIMECCC). The sensors allow asynchronous SEU detection, reducing the time to detect by 57 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$250\times $ </tex-math></inline-formula> on average and enabling local reconfiguration. Our method includes built-in dual redundancy that reduces the power consumption by 87% on average, benefiting embedded systems. SRIMECCC is also an area-efficient technique that saves 28% of total effective area compared to TMRed designs implemented in FPGAs.

Field-programmable gate arrays are susceptible to radiation-induced single event upsets. These are commonly dealt with using triple modular redundancy (TMR) and module-based configuration memory error recovery (MER). By triplicating components and voting on their outputs, TMR helps localise configuration memory errors, and by reconfiguring faulty components, MER swiftly corrects them. However, the order in which TMR voters are checked inevitably impacts the overall system reliability. In this study, the authors outline an approach for computing the reliability of TMR–MER systems that consist of finitely many components. They demonstrate that system reliability is improved when the more vulnerable components are checked more frequently than when they are checked in round-robin order. They propose a genetic algorithm for finding a voter checking schedule that maximises the reliability of TMR–MER systems. Results indicate that the mean time to failure (MTTF) of these systems can be increased by up to 400% when variable-rate voter checking (VRVC) is used instead of round robin. They show that VRVC achieves 15–23% increase in MTTF with a 10× reduction in checking frequency to reduce system power. They also found that VRVC detects errors 44% faster on average than round robin.

Modern SRAM-based field programmable gate array (FPGA) devices offer high capability in implementing complex system. Unfortunately, SRAM-based FPGAs are extremely sensitive to single event upsets (SEUs) induced by radiation particles. In order to successfully deploy safety- or mission-critical applications, designer need to validate the correctness of the obtained designs. In this paper we describe a system based on partial-reconfiguration for running fault-injection experiments within the configuration memory of SRAM-based FPGAs. The proposed fault-injection system uses the internal configuration capabilities that modern FPGAs offer in order to inject SEU within the configuration memory. Detailed experimental results show that the technique is orders of magnitude faster than previously proposed ones.