A low-power 10-bit 250-KSPS cyclic ADC with offset and mismatch correction

The analog-to-digital conversion required in most disk-drive read-channel applications is designed for good dynamic and noise performance over a wide-input frequency range. This paper presents a 500-MSample/s, 6-bit analog to-digital converter (ADC) and its embedded implementation inside a disk-drive read channel, using a 0.35-/spl mu/m CMOS double-poly (only one poly layer was used in the ADC), triple-metal process. The converter achieves better than 5 effective number of bits (ENOB) for input frequencies up to Nyquist frequency (f/sub in/=f/sub s//2) and sampling frequencies f/sub s/ up to 400 MHz. It also achieves better that 5.6 ENOB for input frequencies up to f/sub s//4 over process, temperature, and power-supply variations. At maximum speed (f/sub s/=500 MHz), the converter still achieves better than 5 ENOB for input frequencies up to f/sub in/=200 MHz. Low-frequency performance is characterized by DNL<0.32 LSB and INL<0.2 LSB. The converter consumes 225 mW from a 3.3-V supply when running at 300 MHz and occupies 0.8 mm/sup 2/ of chip area.

This paper proposes a leading-subcycles capacitor error-averaging (LCEA) scheme to reduce the capacitor mismatch error of cyclic analog-to-digital converters (ADCs) while only slightly lowering the conversion rate. The scheme does not need complicated structures or extra calibration circuits. Hence, the proposed LCEA scheme can be used for cyclic ADCs to achieve high accuracy while maintaining their low-power and small-area features. In addition, the figure of merit (FOM) versus the number of averaging operations in a complete conversion cycle is analyzed such that power-accuracy-speed tradeoffs can be optimized. A proof of concept 12-bit cyclic ADC is implemented to compare the performance of the proposed LCEA scheme with that of a conventional cyclic ADC. The chip is fabricated in a 3.3-V, 0.35-μm CMOS process. Measurements demonstrate that the cyclic ADC with only two averaging operations has a 6 dB and 10 dB higher signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR), respectively, than the conventional cyclic ADC, and with only a slightly reduced conversion rate of 12/13 times than that of the conventional cyclic ADC. In addition, the measured FOM is greatly reduced to 0.55 times of that obtained using the conventional scheme which indicates the advantage of the LCEA technique.

A successive approximation register (SAR) analog-to-digital converter (ADC) design in 0.18-um CMOS process is presented for wireless power transfer applications. By applying body effect reduction T/H circuit that improved ENOB of the ADC. This proposed ADC uses asynchronous control logic without off-chip frequency clock. The measured consumption of 1.53 mW at input voltage of 1.8 V, sampling rate of 40 MS/s, the proposed design realizes a spurious-free dynamic range (SFDR) of 62.16 dB, an effective number of bits (ENOB) of 8.93 bits, a signal-to-noise and distortion ratio (SNDR) of 55.52 dB, integral nonlinearity (INL) of 1.12 LSB and differential nonlinearity (DNL) of 0.63 LSB. The proposed SAR ADC is build-in internet of thing (IoT) system to meet low power requirement for wireless power receiver applications.

This paper presents a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) that uses a digital-to-analog converter (DAC) configurable window switching technique. By reusing the capacitors in the DAC, the proposed window switching scheme yields window boundaries to determine whether the input is located within the window, and thus avoid unnecessary capacitor switching. The proposed window SAR ADC improves the conversion efficiency and ADC linearity. A qualitative analysis of prior window switching schemes is presented to elaborate for various applications. A low-input capacitance of 1 pF was adopted to relax the input and reference buffers. A prototype ADC was implemented in 180-nm CMOS occupying an active area of 0.1 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . At 20 MS/s, it consumes a total power of 1.22 mW from a 1.5-V supply. The measured peak signal-to-noise and distortion ratio and spurious-free dynamic range were 61.7 and 79 dB, respectively. At the Nyquist rate, the measured effective number of bits (ENOB) was 9.53, equivalent to a figure-of-merit (FOM) of 83 fJ/conversion-step. In low-power mode (100 kS/s), it consumed a total power of 1.5μW from a 0.7-V supply. At the Nyquist rate, the measured ENOB was 9.82, equivalent to a FOM of 16.6 fJ/conversion step.

Effects of error in code transition levels on nonlinearity and effective number of bits (ENOB) of an analog to digital converter (ADC) are presented in this article. Error in code transition level is determined by deviation of code transition levels from the mean of the estimated code transition levels. Errors in estimate of differential nonlinearity (DNL), integral nonlinearity (INL) and ENOB are computed by considering error in code transition levels and computing corresponding values. In this study, 5- and 8-bit ADC transfer characteristics are simulated and arbitrary nonlinearity errors are introduced. Suitable corrections are applied in code transition levels and computation of estimate of nonlinearity with and without corrections are reported. Results have been compared with earlier published work and improvements are observed. Effects of overdrive and additive noise on ENOB for 5-bit ADC are also reported.

This paper presents an 8-bit 100KS/s successive approximation register (SAR) analog-to-digital convertor (ADC) in SMIC 0.13 µm 1P8M process for biomedical applications. This ADC is implemented with sub-circuits consuming no static power, thereby preserving the desired low power characteristic. According to the measured results, the SAR ADC has a signal-to-noise distortion ratio (SNDR) of 49.2 dB, and the spurious free dynamic range (SFDR) of 63 dB for a 9.37 kHz full-scale input sinusoidal wave at a 100 kHz sampling rate. The effective number of bit (ENOB) is 7.8 bits. The differential nonlinearity (DNL) is in the range of −0.15/+0.15 LSB whereas the integral nonlinearity (INL) is within −0.35/+0.23 LSB. The total power is 3.2uW and the figure of merit (FOM) is 143 fJ/conversion-step.

This paper presents the design of a low-power high-dynamic-range analog-to-digital converter (ADC) for solid-state radiation detectors, in particular Cadmium Zinc Telluride (CZT). The core of the ADC consists of a Wilkinson-type digitizer, a digital control unit and a 9-bit counter. The analog core of the ADC operates from a 3.3 V supply while the supply for the digital control circuitry is 1.2 V. The input dynamic range of the ADC is 2.7 V and the ADC consumes 631 μW. The ADC is designed and laid-out in a standard 0.13-μm CMOS process and occupies 0.026 mm2. Post-layout simulation results show that the signal-to-noise and distortion ratio (SNDR) of the ADC is just over 50 dB which corresponds to an effective number of bits (ENOB) of approximately 8. The simulated differential and integral nonlinearities (DNL and INL) are ±0.065 LSB and 0.954 LSB, respectively.

Digitally-assisted integrated circuit design has gained popularity in recent years due to challenges associated with analog components in mixed-signal systems-on-a-chip, which include process variations, mismatches, and increased demand for circuit complexity in sub-micron fabrication process technologies. To optimize efficiency and cost, the focus during hardware design is increasingly directed on the creation of reliable and robust circuits that are immune to variations and unpredictable factors out of the designer's control. On the other hand, the circuits should be power and area efficient to adapt to the needs associated with portable devices, wireless communications, and the global energy and cost saving trends. On-chip calibration techniques can be developed to address these issues by reducing the sensitivity of analog circuit designs, thereby improving their universal usefulness and scalability. Another emerging trend is the rising demand for high-speed low-power analog-to-digital converters (ADCs) to accommodate the increased use of digital processing and big data. The research described in this thesis unites these topics in a design approach for ADCs. This thesis introduces the design of a 3-bit flash ADC with an offset calibration scheme, which is integrated into a two-step 8-bit hybrid flash/successive approximation register (SAR) architecture with time-interleaving. Due to the hybrid architectural structure, the offset requirement for the flash ADC is more stringent than for a conventional standalone 3-bit ADC. Two pairs of transistors are employed to adjust the offsets for each of the seven comparators in the flash ADC by creating a current flow imbalance between the comparator's branches. The amount of current injected in each branch is controlled through the gate voltages of the calibration transistors, which are generated with automatic on-chip calibration circuitry that was developed as part of this research. The circuits were designed, simulated, and fabricated using 130nm complementary metal-oxide semiconductor (CMOS) technology. The calibration path emulates the ADC's normal operation to establish realistic loading and transient effects. Furthermore, the design approach addresses integration challenges within the hybrid ADC system, such as kickback noise and common-mode variations. Monte Carlo simulation results show that the offset standard variation is reduced from 19.2mV to 0.582mV through the calibration. The power consumption of all digital circuits is 1.36mW from a separate 1.2V supply, and the power consumption of the calibration logic with a 10MHz clock is 0.60mW. The dynamic latched comparator of the flash ADC with kickback reduction was evaluated with post-layout simulations including process-voltage-temperature (PVT) variations. It has a 231ps propagation delay, and consumes 0.16mW. From simulations of the flash ADC, the worst-case effective number of bits (ENOB) is 2.88, and the worst-case signal-to-noise-and-distortion ratio (SNDR) is 19.1dB in the slow process corner case with a temperature of 85 degree Celsius and 1.14V supply. The flash ADC consumes 3.6mW. The comparator design incorporates a kickback reduction technique that reduces the kickback effect from 23.3mV to 1.2mV for a 500mV input during system-level simulations. Measurements of a prototype chip show that the ENOB improves from 3.64 to 5.24 bits using a 500MHz clock during automatic calibration.

In this paper, an approach to estimate signal to noise ratio (SNR) and effective number of bits (ENOB) in nonideal multi-bit stages of pipelined analog to digital converters (ADCs) is presented. The most significant error sources in multistage ADCs are the capacitor mismatch and the finite and imprecise gain of amplifier. Output voltage of each stage in pipelined ADC is modeled by an ideal and a nonideal output, where nonideal output is the error due to circuit imperfections in each stage. Using an appropriate model, the SNR and ENOB due to circuit nonidealities and in terms of standard deviation of random errors are calculated. Simulation results show the accuracy of the analytical proposed approach in estimation of SNR and ENOB in multi-bit per stage pipelined converters.

A 5 GS/s 8-bit analog-to-digital converter (ADC) implemented in 0.18 μm SiGe BiCMOS technology has been demonstrated. The proposed ADC is based on two-channel time-interleaved architecture, and each sub-ADC employs a two-stage cascaded folding and interpolating topology of radix-4. An open loop track-and-hold amplifier with enhanced linearity is designed to meet the dynamic performance requirement. The on-chip self-calibration technique is introduced to compensate the interleaving mismatches between two sub-ADCs. Measurement results show that the spurious free dynamic range (SFDR) stays above 44.8 dB with a peak of 53.52 dB, and the effective number of bits (ENOB) is greater than 5.8 bit with a maximum of 6.97 bit up to 2.5 GS/s. The ADC exhibits a differential nonlinearity (DNL) of -0.31/+0.23 LSB (least significant bit) and an integral nonlinearity (INL) of -0.68/+0.68 LSB, respectively. The chip occupies an area of 3.9 × 3.6 mm2, consumes a total power of 2.8 W, and achieves a figure of merit (FoM) of 10 pJ/conversion step.

A novel digitally assisted high-speed 14-bit pipelined ADC model based on matlab/simulink is proposed. The model consists of a 4-bit first-stage with nonlinearity gain error, a 2-bit second-stage with 1-bit redundancy and five ideal 2-bit stages. A backend calibration technique is used to calibrate the nonlinearity error of the first stage, which significantly improves the Signal Noise Ratio (SNR) and Effective Number of Bit (ENOB) of the Analog-to-Digital Converter (ADC). Simulation results indicate that the maximum SNR and ENOB of this pipeline ADC reach the value of 82dB and 14 bits respectively under the case of the input signal frequency at 9.72MHz and the sampling clock at 100MHz after calibration.

This brief presents a zero-crossing-based pipeline analog-todigital converter (ADC) architecture that can effectively reduce hardware complexity and power consumption for high-speed ADCs. The ADC uses only simple open-loop amplifiers for residue amplification. Using modified sliding interpolation and subranging techniques, the number of amplifiers is reduced by 60%. A 10-bit 200-MS/s ADC, employing the architecture and other techniques, such as double sampling, digital error correction, and source degeneration, is fabricated in 0.13-μm CMOS process and occupies a die area of 0.7 mm2. The differential and integral nonlinearity of the ADC are less than 0.83/-0.47 and 1.05/-0.7 LSB, respectively. With a 1.5-MHz full-scale input, the ADC achieves 56.5-dB signal-to-noise plus distortion ratio, 71.8-dB spurious free dynamic range, and 9.1 effective number of bits at full sampling rate while dissipating 38 mW from a 1.2-V supply.

This paper presents a 12‐bit, high speed charge‐sharing analog‐to‐digital converter (ADC), targeting low area and low power in wide bandwidth integrated RF transceivers for ultrasound diagnostic medical devices. The ADC comprises charge sharing digital‐to‐analog converter (DAC) with unit array capacitors with low threshold voltage devices for small area and low on resistance respectively. The circuit uses sample and hold circuit based on bootstrapping to reduce the effect of third harmonic. The dynamic latch comparator with adaptive power control improves the power efficiency. Furthermore, the asynchronous SAR logic delay cells are digitally controlled to minimize the power consumed by the digital part. The ADC achieves an effective number of bits (ENOB) of 11.40 bits and signal to noise distortion ratio (SNDR) of 70.39 dB at the input frequency of 500 kHz. The designed ADC is implemented with a 0.13 μm CMOS process occupying an area of 1600 μm × 505 μm. The designed SAR ADC draws 0.8 mA current per channel at a sampling rate of 30 MSPS when operated at a 1.5 V power supply.

A 600-MS/s 6-bit folding and interpolation analog-to digital converter (ADC) is presented. This ADC with single track-and-hold (T/H) circuits is based on cascaded folding amplifiers and input-connection-improved active interpolating amplifiers. Under a supply voltage of 1.4 V, the ADC achieves 5.55 bit of effective number of bits (ENOB) and 47.84 dB of spurious free dynamic range (SFDR) at 10-MHz input and 4.3 bit of ENOB and 35.65 dB of SFDR at 200-MHz input with 500-Ms/s sampling rate and achieves 5.48 bit of ENOB and 43.52 dB of SFDR at 1-MHz input and 4.66 bit of ENOB and 39.56 dB of SFDR at 30.1-MHz input with 600-Ms/s sampling rate. Differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.62 LSB and 0.66 LSB, respectively. The circuit is prototyped in 0.13-µm CMOS process and occupies a core area of 0.17 mm2. The converter only dissipates 25 mW1.

This paper presents a 10-bit 100MS/s analog to digital converter (ADC) that based on successive approximation (SAR) algorithm. This ASIC is to fulfill the requirement of Hadronic Calorimeter (HCal) upgrade: custom cost-efficient high sampling digitizer electronics and capable of continuous operation mode. The designed chip is developed by using the TSMC 65nm CMOS technology. The post-layout simulations show this ADC could achieve peak signal to noise and distortion ratio (SNDR) of 58 dB at Nyquist rate input frequency and power consumption of 3.5 mW. The peak effective number of bits (ENOB) is 9.6 bits, equivalent to the figure of merit of 45 fJ/conversion step.