A Low‐Power CMOS‐Only Voltage Reference

A high precision band-gap reference (BGR) with piecewise-linear compensation is designed in this paper. A low voltage Brokaw BGR architecture is employed to provide low output voltage. A high gain, low power supply rejection ratio (PSRR) operational amplifier is designed to improve the PSRR of the band-gap reference. In order to achieve temperature stability significantly lower than the traditional band-gap reference, a circuit which produces a current with positive temperature coefficient (TC) at high temperatures and 0 current at lower temperatures is designed. The whole BGR circuits are simulated by Spectre based on chartered 0.18μm 1P5M 1.8V CMOS technology. It's clear from simulation result that the TC of the output reference voltage approaches 2.61ppm/K over the military temperature range, the PSRR reaches 107.2dB at low frequency (f=0.1HZ), the whole BGR dissipates 0.4mW. In addition, the output reference voltage changes only 8.6μV when the power supply changes from 1.5V to 2.1V, that is to say, the power regulation ratio is 0.014mV/V.

Electromagnetic Interference (EMI) disturbances coupled in the power supply of voltage and current references can severely degrade their performance, due to its finite Power Supply Rejection Ratio (PSRR). The design of a 90 dB PSRR, 4 dBm EMI resistant NMOS-Only Voltage Reference is herein presented. The Voltage Reference is designed based on the Zero Temperature Coefficient (ZTC) transistor point. The high-PSRR is obtained using zero-VT transistors as active loads in the open and feedback loop of the circuit. The final circuit was designed in a 130 nm CMOS process and occupies around 0.014 mm2 of silicon area while consuming just 1.15 μW. Post-layout simulations present a 206 mV of Voltage Reference with a Temperature Coefficient of 321 ppm/°C, for the temperature range from −55 to 125 °C. An EMI source of 4 dBm (1 V pp ) injected in the power supply, according to the Direct Power Injection (DPI) standard, yield in a maximum dc shift and Peak-to-peak ripple of −0.17 % and 822 μV pp , respectively.

A novel 79-nW CMOS-only subthreshold voltage reference with 328-mV output voltage, which works down to 0.8-V supply voltage, is presented in this brief. In order to reduce the area and power consumption, the proposed circuit avoids the use of resistors and bipolar transistors. A current subtracting technique is proposed to realize the temperature compensation of reference current. Instead of the op-amp in traditional circuits, some cascode current mirrors are used to enhance the power supply rejection ratio (PSRR). A novel structure consisting of a 1.8-V MOS transistor and a 3.3-V MOS transistor is utilized to accomplish the voltage temperature compensation and to further reduce the power consumption of VREF generator. The proposed voltage reference was fabricated in 0.18- ${\mu }\text{m}$ CMOS process. The measured results show that the temperature coefficient of the output voltage is 33.8 ppm/°C in the range from 10 °C to 100 °C, the PSRR is −55 dB @ 100 Hz at 1.2-V power supply, and the line regulation is 0.21%/V in a supply voltage range of 0.8 to 3.4 V. What is more, the power dissipation is 79 nW, and the chip area is 0.01 mm2. It is suitable for low-power applications.

Based on the negative temperature characteristics of threshold voltage and positive temperature characteristics of a multiple of thermal voltage, adding them with proper weight coefficient A voltage reference circuit was proposed with a zero temperature coefficient (TC). The device consists of pure MOSFET operated in subthreshold region and uses no resistors and bipolar transistors. The triple-branch current reference structure is adopted for independence of supply voltage instead of cascade structure and embedded operational amplifier structure with the merit of chip area and power consumption. Simulation results showed that based on standard CMOS 0.18 um process, the circuit can operate at 0.75 V supply voltage with the output voltage only 563 mV. The TC of the voltage was 17.5 ppm/℃ in a range from −40 ℃–125 ℃. The line sensitivity was 569.5 ppm/V in a supply voltage range of 1.2 V–1.8 V, and the power supply rejection ratio (PSRR) was 66.5 dB at 100 Hz. The power dissipation was only 187.4 nW.

In this paper, a Bandgap reference (BGR) with high power supply rejection ratio (PSRR) and low temperature coefficient (TC) is presented. On the basis of first-order temperature-compensated BGR, a complementary curvature-compensation technique (CCCT) is realized by using the saturation region current characteristics of PMOS transistors with proportional to absolute temperature (PTAT) bias voltage. Besides, in addition to the effect of cascode structure and the isolation of the current amplifier, the PSRR of proposed BGR is further improved by adopting self-bias power supply with feedback. The presented BGR is implemented in a standard 0.35 μm BCD process. The post-simulation results show that the TC of the BGR is 4.740 ppm/∘C with a 2.50V average output voltage, and the PSRR is up to -78.5dB.

With the recent advancements in ultra-low power wireless devices such as wireless sensor networks, the demand for nanowatt voltage references capable of operating below 1-V becomes a necessity. But due to the low voltage overhead imposed by the supply, most of the recent literatures on sub-1-V voltage references exhibited low power supply rejection ratio (PSRR) and thus were prone to switching noise induced at the supply line. This paper presents a high PSRR, subthreshold MOSFET-only voltage reference which has been simulated in $0.18 \mu\mathrm{m}$ TSMC CMOS process using the Synopsys HSPICE tool. The circuit employed a PSRR enhancement block that suppresses the variation along the supply of the core voltage reference. This circuit block implemented a negative feedback network that regulated the internal supply voltage of the core reference circuit. Simulation results showed that the proposed overall circuit generated an output voltage of 244.5 mV which operated properly at a supply voltage of 0.95-V and achieved a PSRR of −140.6 dB, −101.1 dB, − 64.3 dB, and −38.4 dB at 100 Hz, 1 kHz, 10 kHz, and 10 MHz respectively. The circuit also achieved a temperature coefficient of 9.9 ppm/oC from −25 °C to 100 °C while consuming only 74.6 nW. From these results, the designed high PSRR voltage reference provides the necessary specifications suitable for wireless sensor network nodes.

0.7-V supply, 21-nW All–MOS voltage reference using a MOS-Only current-driven reference core in digital CMOS

This paper presents a curvature-compensated bandgap circuit processed in a double- metal 0.8 /spl mu/m CMOS technology. The circuit has a reference voltage of 1 V, and it operates with supply voltages higher than 1.6 V, consuming 8 /spl mu/A at room temperature. An ultimate simple technique is used for curvature compensation. The temperature coefficient is 10 ppm/K, and the power supply rejection ratio is 66 dB. The circuit can be used in LDOs, reset controllers and other low-voltage analog and mixed signals ICs.

This paper presents a high wide band power supply rejection ratio (PSRR) current mode bandgap reference (BGR) with a fast startup performance. The BGR includes three main enhancement techniques to improve the PSRR. The proposed design is implemented in 130nm CMOS technology. It only consumes 50μA from a 1.8V supply. The BGR provides 850mV reference voltage and has a power supply rejection ratio (PSRR) of 130dB from DC to 100Hz and more than 110dB till 100MHz. The temperature coefficient (TC) is 10 ppm/°C from -40°C to 125° C. The Bandgap start-up time is 70ns.

A novel band-gap reference circuit is presented in order to reduce the offset voltage and power consumption. By using the op-amp input voltage as part of the reference voltage source, the gain and power supply rejection ratio of the op-amp is increased. The working principle of the Band-gap reference circuit is analyzed, and it is pointed out that the temperature coefficient becomes smaller through using the temperature compensation. The simulation results based on xiyue 0.3um bipolar process show that the circuit has low power dissipation and good temperature characteristic, the power supply rejection ratio is up to 92dB. The correctness of the theoretical analysis is verified by simulation results.

An extremely low power voltage reference without resistors is presented for power-aware ASICs. In order to reduce the power dissipation, an Oguey current reference source is used to reduce the static current; a cascode current mirror is used to increase the power supply rejection ratio (PSRR) and reduce the line sensitivity of the circuit. The voltage reference is fabricated in SMIC 0.18-μm CMOS process. The measured results for the voltage reference demonstrate that the temperature coefficient of the voltage is 66 ppm/°C in a range from 25 to 100 °C. The line sensitivity is 0.9% in a supply voltage range of 1.8 to 3.3 V, and PSRR is −49 dB at 100 Hz. The power dissipation is 200 nW. The chip area is 0.01 mm2. The circuit can be used as an elementary circuit block for power-aware ASICs.

A low dropout (LDO) voltage regulator with high power supply rejection ratio (PSRR) and low temperature coefficient (TC) is presented in this paper. Large 1µF off-chip load capacitor is used to achieve the high PSRR. However, this decreases the gain and pushes the LDO’s output pole to lower frequency causing the circuit to become unstable. The proposed LDO uses rail-to-rail folded cascode amplifier to compensate the gain and stability problems. 2nd order curvature characteristic is used in bandgap voltage reference circuit that is applied at the input of the amplifier to minimize the TC. The characteristic is achieved by implementing MOSFET transistors operate in weak and strong inversions. The LDO is designed using 0.18µm CMOS technology and achieves a constant 1.8V output voltage for input voltages from 3.2V to 5V and load current up to a 128mA at temperature between -40°C to 125°C. The proposed LDO is targeted for RF application which has stringent requirement on noise rejection over a broad range of frequency.

The power supply rejection ratio (PSRR) of operational amplifiers is analyzed. An analyzing technique based on cuts in subcircuits is presented. The technique allows hand calculation of the PSRR of any circuit. It is shown that the PSRR of the single-stage operational amplifier (OTA) is one order of magnitude better than the commonly used Miller OTA. The analyses are compared with hand calculations and SPICE level-2 simulations on a realized improved Miller OTA structure.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

This paper presents an operational-transconductance-amplifier (OTA) for ultra-low power applications with high CMRR (common mode rejection ratio) and PSRR (power supply rejection ratio). The proposed OTA is a three-stage design. In order to attain the lower supply voltage and high CMRR, a bulk-driven differential pair with the tail current source has been considered as the first stage. The current mirror biasing technique makes sure that all the transistors operate in subthreshold region. A common source amplifier has been opted with current mirror as a load in second stage. At last, common source inverting amplifier is third stage of the designed OTA. The circuit has been designed and synthesized using cadence virtuoso simulator in 180 nm CMOS technology. It has been found that these stages are helpful in achieving high low-frequency gain. Hence, CMRR and PSRR also increase in significant amount. The results describe that the proposed design offers low-frequency gain of 58 dB with CMRR of 72 dB and PSRR of 56 dB for a supply voltage (\( V_{DD} \)) of 0.5 V. The proposed OTA provides the power dissipation of 1.8 µW at \( V_{DD} \) = 0.5 V. Also, the low-frequency gain of 57 dB, CMRR of 70 dB and PSRR of 55 dB with a power dissipation of 2.5 µW have been measured at \( V_{DD} \) = 0.6 V.

This paper presents an ultra-low-power voltage reference designed in 180 nm CMOS technology. To achieve near-zero line sensitivity, a two-transistor (2-T) voltage reference is biased with a current source to cancel the drain-induced barrier-lowering (DIBL) effect of the 2-T core, thus improving the line sensitivity. This compensation circuit achieves a Monte-Carlo-simulated line sensitivity of 0.035 %/V in a supply range of 0.6 to 1.8 V, while generating a reference voltage of 307.8 mV, with 21.4 pW power consumption. The simulated power supply rejection ratio (PSRR) is −54 dB at 100 Hz. It also achieves a temperature coefficient of 24.8 ppm/°C in a temperature range of −20 to 80 °C, with a projected area of 0.003 mm2.