A Method Constructing Orthogonal Latin Squares Based on Complete Y-Matrixes

Objective. Formation of structurally perfect orthogonal Latin squares by the method of index ordering of the multiplication table elements of n-sets based on the multiplication table. Methods. Orthogonal Latin squares are formed by the method of index structuring of n-set multiplication tables. Results. A method is proposed for constructing structurally perfect orthogonal Latin squares of pairs of indexed finite sets of odd dimension, based on the index ordering of an nxn-array of elements in the multiplication table. A distinctive feature of the proposed method for constructing structurally perfect orthogonal squares from elements of two indexed sets of the same dimension is the use by the authors of the method of permutations of elements of the original nxn-matrix configurations, with the formation of index-ordered or index-structured combinatorial configurations. Conclusion. The use of the method for constructing a family of orthogonal Latin squares for pairs of indexed finite sets of the same odd dimension by the elements forming their multiplication table by the method of index structuring based on the principle of functional dependency of the index values on pairs of set elements and index values on pairs of elements from its environment allows creating a specific class orthogonal configuration, which, in terms of element indices, easily demonstrates their orthogonality.

The use of error-correcting codes is a common strategy to protect memories from errors. Single-error correction, double-error detection linear block codes have been traditionally utilized. However, there are applications where multiple errors are frequent and more complex codes are needed. Orthogonal Latin square codes are one type of codes with multiple-error-correction capability. They are of interest for memory protection because they can be decoded with low complexity and delay. This paper presents a modification to orthogonal Latin square codes that reduces the number of parity check bits to be stored in memory therefore lowering the memory overhead needed to implement the codes. The proposed codes can also be decoded with low delay and complexity. This paper also presents an evaluation of the encoder and decoder implementations for various word sizes and compares them with the standard orthogonal Latin square implementations. The results show that they are similar in terms of circuit area and introduce only a small penalty in delay.

Analysis of covariance (ancova) is a technique that combines features of analysis of variance and regression which is used to increase precision (accuracy) of the experiment. Ancova can be used for any experimental design include Graeco Latin square design. Graeco Latin square design is a combination of two orthogonal Latin square. Two Latin square are orthogonal if they are combined, the same pair of symbols occurs no more than once in the composite square. Application ancova on Graeco Latin square design in the field of agriculture is given to observe the effect of different fertilizer dose towards outcome of corn production. In this experiment there are three blocking factors (soil pH, soil slopes, and corn varieties) and two variable concomitant (quantity of corn plant and quantity of baby corn). The result shows that both of concomitant variables effect are significant. Ancova is better than anova, it can see from the coefficient of variation ancova less than anova, so precision (accuracy) of the experiment is increase. That is why concomitant variable can’t be ignored from the experiment. Keywords : Analysis of Covariance (ancova), Analysis of Variance (anova), Analysis Regression, Graeco Latin square design, Orthogonal.

The problems relating to the existence and construction of orthogonal Latin squares have fascinated researchers for several centuries now. Though many important discoveries have been made, some problems still remain unresolved. Latin squares and orthogonal Latin squares have a beautiful underlying structure and are related to other combinatorial objects. These have applications in different areas, including statistical design of experiments and cryptology. Comprehensive accounts of the theory and applications of Latin squares are available in the books by J. Dénes and A. D. Keedwell (1974, 1991) and C. F. Laywine and G. L. Mullen (1998).

Nearly orthogonal Latin squares are useful for conducting experiments eliminating heterogeneity in two directions and using different interventions each at each level. In this paper, some constructions of mutually nearly orthogonal Latin squares are provided. It is proved that there exist 3 MNOLS(2m) if and only if m ≥ 3 and there exist 4 MNOLS(2m) if and only if m ≥ 4 with some possible exceptions.

SUMMARY Three theorems on the construction of orthogonal latin squares are presented. The first describes a general procedure for constructing orthogonal latin squares of odd order. The second theorem proves that the procedure of theorem one fails for some families of latin squares of even order. The last theorem demonstrates that certain families of latin squares of even order are orthogonally mateless.

Fast color image encryption scheme based on 3D orthogonal Latin squares and matching matrix

Conjugate Orthogonal Latin Squares with Equal-sized Holes

Radiation-induced soft errors are a major reliability concern for memories. To ensure that memory contents are not corrupted, single error correction double error detection (SEC-DED) codes are commonly used, however, in advanced technology nodes, soft errors frequently affect more than one memory bit. Since SEC-DED codes cannot correct multiple errors, they are often combined with interleaving. Interleaving, however, impacts memory design and performance and cannot always be used in small memories. This limitation has spurred interest in codes that can correct adjacent bit errors. In particular, several SEC-DED double adjacent error correction (SEC-DED-DAEC) codes have recently been proposed. Implementing DAEC has a cost as it impacts the decoder complexity and delay. Another issue is that most of the new SEC-DED-DAEC codes miscorrect some double nonadjacent bit errors. In this brief, a new class of SEC-DED-DAEC codes is derived from orthogonal latin squares codes. The new codes significantly reduce the decoding complexity and delay. In addition, the codes do not miscorrect any double nonadjacent bit errors. The main disadvantage of the new codes is that they require a larger number of parity check bits. Therefore, they can be useful when decoding delay or complexity is critical or when miscorrection of double nonadjacent bit errors is not acceptable. The proposed codes have been implemented in Hardware Description Language and compared with some of the existing SEC-DED-DAEC codes. The results confirm the reduction in decoder delay.

Adaptive error correction in Orthogonal Latin Square Codes for low-power, resilient on-chip interconnection network

In recent years, there has been a growing interest in multi-bit error correction codes (ECCs) to protect SRAM memories. This has been caused by the increased number of multiple errors that memories suffer as technology scales. To be suitable to protect an SRAM memory, an ECC has to be decodable in parallel and with low latency. Among the codes proposed for memory protection are orthogonal latin square (OLS) codes that provide low latency decoding and a modular construction. For some applications, like multimedia or signal processing, the effect of errors on the memory bits can be very different depending on their position on the word. Therefore, in these cases, it is more effective to provide different degrees of error correction for the different bits. This is done with unequal error protection (UEP) codes. In this paper, UEP codes are derived from double error correction (DEC) OLS codes. The derived codes are implemented for an FPGA platform to evaluate the decoder complexity and latency. The results show that the new codes can be implemented with lower decoding delay than traditional SEC-DED codes and with a cost similar to that of both DEC OLS and SEC-DED codes.

This paper deals with the search for triples of partially orthogonal Latin squares of order 10. For every known pair of orthogonal Latin squares of order 10 we add a third diagonal Latin square in such a way that the orthogonality condition between it and squares from a considered pair coincides in the maximum possible number of cells. Two approaches are used: the first one is based on reducing an original problem to Boolean satisfiability problem; the second one is based on Brute force method. Several triples of the aforementioned kind with high characteristics were constructed. The experiments were held in the volunteer computing project SAT@home and on a computing cluster.

This paper presents a concurrent error detection (CED) scheme for orthogonal Latin square (OLS) parallel decoders. Different from a CED scheme found in the technical literature that protects only the syndrome generator, the proposed CED scheme protects the whole OLS decoder for single stuck-at faults. This paper presents the detailed design and analysis of the proposed CED scheme and shows that it is strongly fault secured for single stuck-at faults. Extensive simulation results are also provided; different figures of merit such as area, power dissipation, gate depth, and coverage are assessed. It is shown that the proposed decoder designs for ( n, k) t-bit error correcting OLS codes (k = 16 ...256; t = 2 ...5) have reasonable overhead; for example, the average area overhead of the proposed CED is 35.5 (23.6) % compared with an OLS decoder with no CED (i.e., the previously reported CED scheme). However, the most significant advantage of the proposed scheme is that it achieves 100% fault coverage for the whole CED circuit, thus providing a very efficient and fully fault-tolerant implementation. The proposed CED is applicable to both binary and nonbinary OLS codes; the CED for a nonbinary OLS decoder achieves comparable or better results than a binary OLS decoder. Moreover, simulation shows that the proposed CED scheme is better than double modular redundancy.

The benefits of the continued progress in integrated circuit manufacturing have been numerous, most notably in the explosion of computing power in devices ranging from cell phones to cars. Key to this success has been strategies to identify, manage, and mitigate yield loss. One such strategy is the use of test structures to identify sources of yield loss early in the development of a new manufacturing process. However, the aggressive scaling of feature dimensions, the integration of new materials, and the increase in structural complexity in modern technologies has challenged the capabilities of conventional test structures. To help address these challenges, a new logic test chip, called the Carnegie Mellon Logic Characterization Vehicle (CM-LCV), has been developed. The CM-LCV utilizes a two- dimensional array of functional unit blocks (FUBs) that each implement an innovative functionality. Properties including fault coverage, logical and physical design features, and fault distinguishability are shown to be composable within the FUB array; that is, they exist regardless of the size and composition of the FUB array. A synthesis ow that leverages this composability to adapt the FUB array to a wide range of test chip design requirements is presented. The connection between the innovative FUB functionality and orthogonal Latin squares is identified and used to analyze the universe of possible FUB functions. Two additional variants to the FUB array are also developed: heterogenous FUB arrays utilize multiple FUB functions to improve the synthesis ow performance, while pipelined FUB arrays incorporate sequential circuit elements (e.g., ip- ops and latches) that are absent from the original combinational FUB array. In addition to the design of the CM-LCV, methods for testing it are presented. Techniques to create minimal sets of test patterns that exhaustively exercise each FUB within the FUB array are developed. Additional constraints are described for the heterogenous and pipelined FUB arrays that allow these techniques to be applied for both variant FUB arrays. Furthermore, a simple built-in self test (BIST) scheme is described and applied to a reference design, resulting in a 88.0% reduction in the number of test cycles required without loss in fault coverage. A hierarchical FUB array diagnosis methodology (HFAD) is also presented for the CM- LCV that leverages its unique properties to improve performance for multiple defects. Experiments demonstrate that this HFAD methodology is capable of perfect accuracy in 93.1% of simulations with two injected faults, an improvement on the state-of-the-art commercial diagnosis. Additionally, silicon fail data was collected from a CM-LCV manufactured using a 14nm process by an industry partner. A comparison of the diagnosis results for the 1,375 fail logs examined shows that the HFAD methodology discovers additional defects during multiple defect diagnosis that the commercial tool misses for 40 of the diagnosed fail logs. Examination of these cases shows that the additional defects found by the HFAD methodology can result in improved diagnosis confidence and more precise descriptions of the defect behavior(s). The contributions of this dissertation can thus be summarized as the description of the design, test, and diagnosis of a new logic test chip for use in yield learning during process development. This CM-LCV can be adapted to meet a wide range of test chip requirements, can be efficiently and rigorously tested, and exhibits properties that can be used to improve diagnosis outcomes. All of these claims are validated through both simulated experiments and silicon data.

On the orthogonal Latin squares polytope