1- https://doi.org/10.1007/978-0-387-34892-6_26
A methodology for the implementation of protocols in hardware from a formal description
- Jan 1, 1996
- L Pirmez +2 more
Abstract
A methodology1 that efficiently translates Estelle formal specifications into a Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) description, suitable for the high level syntesis of an integrated circuit, is proposed. It will be shown that, in order to efficiently map Estelle into VHDL, a number of constrains must be imposed on the set of possible constructs within each language. An example based on the specification of a high speed protocol is discussed.
- # Very High Speed Integrated Circuit ) Hardware Description Language
- # Very High Speed Integrated Circuit
- # Protocols In Hardware
- # Hardware Description Language
- # Formal Description
- # Estelle Specifications
- # High Speed
- # Specification Of Protocol
- # Description Language
- # Circuit Hardware
