A Multi-valued Algebra for Capacitance Induced Crosstalk Delay Faults

A hybrid DFT method is proposed to reduce the hardware penalty of traditional DFT methods and test generation time. It takes advantages of both traditional DFT methods like scan and DFT methods which control clocks for testability. The hardware scheme and test generation algorithm are presented. Test generation results for ISCAS '89 circuits have been generated and showed an improvement in test generation time and fault coverage.

In this paper a method for high-level test generation for systems described in VHDL is presented. First, two test generation algorithms for VHDL processes are presented. The first algorithm works on processes which represent combinational logic whereas the second works on processes which represent sequential logic. The goal of both algorithms is to test all portions of the process body by traversing all the feasible paths. Employing these two algorithms, two new algorithms for system-level test generation for both combinational and sequential systems are presented. The approach employs software metrics as well as signal coverage for interconnections and state and transition coverage for FSMs.

In the context of automatic test generation, the use of propositional satisfiability (SAT) and Satisfiability Modulo Theories (SMT) solvers is becoming an attractive alternative to traditional algorithmic test generation methods, especially when testing Boolean expressions. The main advantages are the capability to deal with constraints over the inputs, the generation of compact test suites and the support for fault-detecting test generation methods. However, these solvers normally require more time and a greater amount of memory than classical test generation algorithms, making their applicability not always feasible in practice. In this paper, we propose several ways to optimize the SAT/SMT-based process of test generation for Boolean expressions and we compare several solving tools and propositional transformation rules. These optimizations promise to make SAT/SMT-based techniques as efficient as standard methods for testing purposes, especially when dealing with Boolean expressions, as proved by our experiments.

Scan design has been widely used for alleviating the burden of test generation. How to reduce the extra costs caused by the scan design becomes a major target now. Previous approaches have tried individually to enhance the abilities of test generation algorithm and scan cell selection strategy. In contrast, a global strategy taking care of the close relationship between these factors and combining a new scan structure is proposed in this paper. Reducing the test application time which may dominate the cost testing a mass product is the goal of this research. First of all, a new scan structure named gradually-on (GO) structure which allows for the scan cells in the scan chain to be gradually turned on is used. Two assertions for the design of test generator are proposed next, and a fault list oriented test generation algorithm is developed in accordance with these two assertions. A simulation based partial scan methodology is finally introduced for selecting the suitable scanning flip-flops one by one through the means of sufficiently utilising the dynamic information generated during fault simulation. Experimental results show that overall consideration of scan design and test generation is able to speed up test generation and reduce a great amount of test application time

Due to the complexity of test generation for stuck-at-faults in synchronous sequential circuits and the permanently increasing problem-size, algorithms solving this problem cannot work with acceptable CPU-time, even on computer systems with very high performance. Relating to this context this paper presents a new testability analysis guiding algorithms for sequential test generation. This testability analysis consists of two separated parts: First, a new technique for the detection of untestable stuck-at-faults; second, heuristics used to guide the decision process in test generation algorithms. Experimental results of sequential benchmark circuits allow us to conclude that our testability analysis provides less CPU-time for sequential test generation than other well-known testability analysis tools. >

A complete system which takes the test generation algorithm, the scan cell selection strategy and the structure of the scan chain into account is proposed. It is totally different from the traditional approaches which try to enhance the ability of the individual subject. The goal of this research is to reduce the extra costs caused by the scan design, especially the test application time. Experimental results show that the overall consideration of scan design and test generation can speed up test generation and greatly reduce the amount of test application time.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Test generation algorithms are being developed with the continuous creation of incredibly sophisticated computer systems. Although dozens of algorithms have been proposed to cope with these issues, there still remains much to be desired in solving such problems as to determine: which of the existing test generation algorithms could be the most efficient for some particular sequential circuits because different algorithms will be better in different circuits; which testability parameters will have the most or the least influences on test generations so that the designers of circuits can have a global understanding during the designing stage. Testability predicting methodology for sequential circuits using a neural network model has been presented, which a user usually needs for analyzing his/her own circuits and selecting the most suitable test generation algorithm from all the possible algorithms they have, and which a designer for VLSI circuits always needs for making his/her circuits being designed more testable.

Current test generation algorithms for path delay faults assume a variable-clock methodology for test application. Two-vector test sequences assume that the combinational logic reaches a steady state following the first vector before the second vector is applied. While such tests may be acceptable for combinational circuits, their use for nonscan sequential circuit testing is impractical. A rated-clock path delay simulator shows a large drop in coverage for vectors obtained from existing test generators that assume a variable clock. A new test generation algorithm provides valid tests for uniform rated-clock test application. In this algorithm, signals are represented for three-vector sequences. The test generation procedure activates a target path from input to output using the three-vector algebra. For an effective backward justification, we derive an optimal 41-valued algebra. This is the first time, rated-clock tests for large circuits are obtained. Results for ISCAS-89 benchmarks show that rated-clock tests cover some longest, or close to longest, paths.

Threshold testing, which is an LSI testing method based on the acceptability of faults, is effective in yield enhancement of LSIs and selective hardening for LSI systems. In this paper, we propose test generation models for threshold test generation. Using the proposed models, we can efficiently identify acceptable faults and generate test patterns for unacceptable faults with a general test generation algorithm, i.e., without a test generation algorithm specialized for threshold testing. Experimental results show that our approach is practically effective.

Hardware testing is a process aimed at detecting manufacturing faults in integrated circuits. To measure test quality, two main metrics are in use: fault detection abilities (fault coverage) and test application time (test length). Many algorithms have been suggested for test generation; however, no scalable solution exists. In this paper, we analyze applicability of functional tests generated from high-level models for low-level manufacturing testing. A particular test generation method is considered. The input information is an HDL description. The key steps of the method are system model construction and coverage model construction. Both models are automatically extracted from the given description. The system model is a representation of the design in the form of high-level decision diagrams. The coverage model is a set of LTL formulae defining reachability conditions for the transitions of the extended finite state machine. The models are translated into the input format of a model checker. For each coverage model formula the model checker generates a counterexample, i.e. an execution that violates the formula (makes the corresponding transition to fire). The approach is intended for covering of all possible execution paths of the input HDL description and detecting dead code. Experimental comparison with the existing analogues has shown that it produces shorter tests, but they achieve lower stuck-at fault coverage comparing with the dedicated approach. An improvement has been proposed to overcome the issue.

This paper presents a method of broadside transition test generation for partial scan circuits. The proposed method first transforms the kernel circuit of a given partial scan circuit into some combinational circuits. Then, by performing stuck-at test generation on the transformed circuits, broadside transition tests for the original circuit are obtained. This method allows us to use existing stuck-at test generation tools in order to generate broadside transition tests. It is shown that the proposed scheme is effective in area overhead and test generation time by experiments. In this paper, some variations of broadside transition testing of partial scan circuits are also discussed in terms of different test application strategies and fault sizes.

The author presents a method for generating test sequences to detect delay faults in sequential circuits using the stuck-at-fault sequential test generator STALLION. The method is complete in that it will generate a delay test sequence for a targeted fault given sufficient CPU time, if such a sequence exists. Faults for which no delay test sequence exists are termed sequentially delay redundant. The author describes means of eliminating sequential delay redundancies in logic circuits. He presents a partial-scan methodology for enhancing the testability of difficult-to-test or untestable sequential circuits, wherein a small number of flip-flops are selected and made controllable/observable. The selection process guarantees the elimination of all sequential delay redundancies. It is shown that an intimate relationship exists between state assignment and delay testability of a sequential machine. A state assignment algorithm for the synthesis of sequential machines with maximal delay fault testability is described. Preliminary experimental results using the test generation, partial-scan, and synthesis algorithms are presented. >

This paper proposes a test generation algorithm combining genetic algorithm for fault diagnosis on linear systems. Most test generation algorithms just used a single value fault model. This test generation algorithm is based on a continuous fault model. This algorithm can improve the treatment of the tolerance problem, including the tolerances of both normal and fault parameters, and enhance the fault coverage rate. The genetic algorithm can be used to choose the characteristic values. The genetic algorithm can enhance precision of test generation algorithm especially for complex fitness functions derived from complex systems under test. The genetic algorithm can also further improve the fault coverage rate by reducing the loop number of divisions of the initial fault range. The experiments are carried out to show this test generation algorithm with a linear system and an integrated circuit.

Increasingly, VLSI systems are being designed using macro blocks and predesigned cores. Since the clock rate at which these circuits operate is steadily increasing, it is important to perform delay testing on modern VLSI chips and systems. Algorithms for delay test generation and delay fault simulation are known to be compute-intensive. Many of these algorithms require gate-level descriptions of circuits which are difficult to generate and may be even impossible to provide when the designer has made use of predesigned cores. Hierarchical testing appears to be an attractive alternative in such cases. Tests generated for logic blocks may be reused to generate tests for larger systems comprising of the logic blocks, hence reducing the total effort in test generation. Tests show in this paper that the computational effort spent in fault simulation can also be reduced using a hierarchical approach. The simulator HIDEFS described in this paper exploits the modular nature of the circuit to save on the memory requirement as well as execution time requirement of fault simulation.

High quality test cases can effectively detect software errors and ensure software quality. However, except the regular expression-based test generation method, test cases generated from other model-based test generation methods have not contain the whole information of the model, resulting in test inadequacy. And test cases derived from regular expression have the prohibited lengths that cause the sustainable increase of test cost. To obtain high quality test cases, we suggest a new method for test generation by way of regular expression decomposition. Unlike the previous model decomposition techniques, our method lays emphasis on information completeness after regular expression is decomposed. Based on two empirical assumptions, we propose two processes of regular expression decomposition and three decomposition rules. Then we perform a case study to demonstrate our approach. The results show that our approach generates high quality test cases as well as avoids the problem of test complexity.