6- https://doi.org/10.1109/icsi.1990.138662
A new arbitration circuit for synchronous multiple bus multiprocessor systems
- Mar 1, 1990
- S.m Mahmud +1 more
Abstract
A novel design for an M-user B-server arbiter for a multiple bus system is presented. The arbitration circuit maintains fairness when it is used in a low-order interleaved memory system. The arbiter is also fair for a general-purpose multiprocessor system where the memory modules are uniformly accessed by the processors. The arbitration time grows at a rate O(log/sub 2/ M), where M is the number of memory modules in a system. When a system has more than four memory modules, both the gate count and delay of the present design are less than those of previous designs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
- # Number Of Memory Modules
- # Memory Modules
- # Arbitration Circuit
- # Multiple Bus
- # Gate Count
- # Multiprocessor System
- # Gate Delay
- # Synchronous Systems
- # Multiple System
- # Multiple Bus Multiprocessor Systems
