A new method for mass fabrication of metallic microstructures

Arrays of silicon nanowire/multiwalled carbon nanotube nanocomposite have been synthesized by wet etching through electroless metal deposition and chemical vapor deposition. Vertically aligned Si nanowire arrays with controlled diameter and length were fabricated by Ag nanodendrite-assisted wet chemical etching of n-type or p-type silicon wafers using HF/ AgNO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> solution. The composite structure was synthesized by formation of a sheath of carbon multilayers on a Si nanowire template surface through a thermal CVD process under various conditions. The results of Raman spectroscopy, scanning electron microscopy and high resolution transmission electron microcopy reveal that the obtained nanocomposite has a silicon nanowire core/carbon nanotube shell structure. Nanocomposite arrays showed good electrochemical properties.

Metallization plays a key role in the production process of integrated devices. Recently, copper (Cu) has been proposed as an alternative material to aluminum to address the need for metallic thin films with low resistivity and high electromigration resistance. 1 As a consequence, great attention has been paid to electrochemical processes, which enable the deposition of metallic copper at low temperatures with low costs. Copper electroless deposition has been shown to selectively plate silicon (Si) substrates and structures with high aspect ratios and large structural heights. 2,3 However, this method requires a pretreatment to activate the surface. Selectivity is achieved only to the extent that the activating treatment can be made selectively. In addition, many studies have also been carried out on the galvanic deposition of copper from fluoride containing solutions.4-11 In contrast to electroless deposition, galvanic displacement deposition requires no prior activation of the surface and is truly selective to silicon surfaces. Thus, it provides an attractive deposition method for copper interconnects or seed layers for subsequent metallization.4 Galvanic displacement is also a promising avenue for the integration of metals in micromechanical devices, due to its conformal nature and high substrate selectivity. Despite these attractive features, a crucial issue in the aforementioned processes is the lack of adhesion of copper to the Si substrate, which may severely constrain their application. 12 In particular, copper films deposited by galvanic displacement fail the qualitative Scotch tape test. In this paper, we report a process for the galvanic deposition of copper onto silicon from fluoride-containing solutions. Thin copper films with reflective and smooth surfaces and excellent adhesion to silicon are obtained. Results on plating of microelectromechanical systems (MEMS) after release are also presented. Polycrystalline silicon and single crystalline Si(100) and Si(111), p- or n-type, and analytical grade chemicals were used. Samples were ultrasonicated in acetone and, after drying with nitrogen flux, etched in concentrated hydrofluoric acid for 10 min. The hydrogenterminated surfaces thus obtained were rinsed, dried, and immersed in the plating solution. The following additives were used to prepare the aqueous solution: ammonium fluoride (NH 4 F 40%) 50 vol %, copper sulfate (CuSO 4 ·5H 2 O) 0.01 M, ascorbic acid (C 6 H 8 O 6 ) 0.01 M, sodium potassium tartrate (KNaC 4 H 4 O 6 ·4H 2 O) 0.005 M, and methanol 30 vol % (percentages are referred to the final solution volume).13 The pH of the solution was 7.5. Room temperature (25°C) and gentle agitation of samples were used. Samples were finally rinsed in deionized water and dried with nitrogen flux. The adhesion of the copper film to the substrate is strongly related to the presence of ascorbic acid in solution. The absence of the acid results in the formation of a copper film which fails the standard scotch tape test. Because we have observed a similar effect when ascorbic acid was substituted with fumaric acid, and both acids are

Surface modification of polyethylene naphthalate substrates by ultraviolet light-irradiation and assembling multilayers and their application in electroless deposition: The chemical and physical properties of the stratified structure

Silver localization on polyimide using microcontact printing and electroless metallization

Individual multi-walled carbon nanotubes (CNTs) were deposited onto microelectrodes and embedded in nickel to achieve low-ohmic contact resistances. Electroless deposition of nickel onto gold/iron, palladium, and cobalt microelectrodes was used to form electrically stable bonds at the interfaces between the electrodes and CNTs. Resistance measurements showed that the contact resistances of the CNTs on gold/iron and palladium were significantly improved by nickel embedding, whereas no further improvement was found for the CNTs on cobalt. Electroless metal deposition is a parallel process providing stable electrical and mechanical contacts between CNTs and metallic microelectrodes.

This work presents a simple and versatile approach for the growth of in-situ contacted single-walled carbon nanotubes (SWCNTs) and subsequent improvement of the contacts using a self-aligned process. We investigated the conditions for the thermal CVD growth of SWCNTs and developed a variety of multilayered metal systems for SWCNT growth at temperatures between 650 °C and 900 °C. The catalytically active layers were either an Fe/Mo bilayer or a Co layer. Further, we report that some of the multilayer systems presented allow lithography free contact improvement by electroless metal deposition.

The colorless square-planar cluster [CuN(SiMe3)2] 4, which contains four Cu(I) ions with four bridging amide groups, was studied as a precursor for chemical and photochemical vapor deposition of Cu metal. The cluster phosphoresces in CH2Cl2 solution and in the solid state at room temperature. Its electronic spectrum in CH 2Cl2 consists of two intense bands which are assigned to symmetry-allowed 3d → 4p transitions; the phosphorescence is also likely to be metal-centered. Solid [CuN(SiMe3)2]4 luminesces with approximately the same spectrum as that of the CH2Cl2 solutions. At 77 K, the solid-state luminescence red-shifts slightly. The emission lifetime in glassy Et2O solution is 690 mus. [CuN(SiMe3) 2]4 deposits Cu metal via chemical vapor deposition under H2 carrier gas at substrate temperatures of 145--200°C. Deposition also occurs photochemically beginning at 136--138°C under near-UV irradiation. The preparation of monomeric derivatives of [CuN(SiMe3) 2]4 was attempted by using neutral donor ligands L (e.g. LnCuN(SiMe3)2; L = CO, PR3, CN-t-Bu; n = 1--3). The target compounds were expected to be more volatile than the copper cluster and still maintain photosensitivity. CuCl and [Cu(CH 3CN)4]PF6 were used as starting materials. Even in the presence of L, [CuN(SiMe3)2] 4 is a major product in reactions using CuCl and NaN(SiCH3) 2- [Cu(CH3CN)4]PF6 was a promising route for the monomeric Cu(I) complexes because of ready dissociation of its acetonitrile ligands. However, the characterization of these complexes was unsuccessful. Other Cu(I) amide clusters have been prepared; they may also be suitable for chemical and photochemical vapor deposition of Cu. [CuNEt2] 4, [CuN(i-Pr)2]4, and [CuN(t-Bu)(SiMe 3)]4 are phosphorescent though they are very air sensitive. They should be more volatile and produce Cu metal films more readily than [CuN(SiMe3)2]4 Cu(hfac)2 is a versatile Lewis acid, forming adducts with a variety of bases. The bases that were used were ethylene glycol, 2-methoxyethanol, propylene glycol, and 1-methoxy-2-propanol. Each Cu(hfac)2 adduct deposited Cu metal under H2 gas at a substrate temperature of 200°C and precursor temperature of 80°C. In contrast to previously known adducts with alcohols, the new precursors do not require excess alcohol vapor for stability. Nevertheless, no Cu deposition was observed with these precursors in the absence of H2 at temperatures up to 135°C.

Two major research areas pertinent to microelectromechanical systems (MEMS) materials and material surfaces were explored and developed in this 5-year PECASE LDRD project carried out by Professor Roya Maboudian and her collaborators at the University of California at Berkeley. In the first research area, polycrystalline silicon carbide (poly-SiC) was developed as a structural material for MEMS. This material is potentially interesting for MEMS because compared to polycrystalline silicon (polysilicon), the structural material in Sandia National Laboratories' SUMMiTV process, it may exhibit high wear resistance, high temperature operation and a high Young's modulus to density ratio. Each of these characteristics may extend the usefulness of MEMS in Sandia National Laboratories' applications. For example, using polycrystalline silicon, wear is an important issue in microengines, temperature degradation is of concern in thermal actuators and the characteristics of resonators can be extended with the same lithography technology. Two methods of depositing poly-SiC from a 1,3-disilabutane source at 650 C to 800 C by low-pressure chemical vapor deposition (LPCVD) were demonstrated. These include a blanket method in which the material is made entirely out of poly-SiC and a method to coat previously released and fabricated polysilicon MEMS. This deposition method is much simpler to use than previous methods such as high temperature LPCVD and atmospheric CVD. Other major processing issues that were surmounted in this LDRD with the poly-SiC film include etching, doping, and residual strain control. SiC is inert and as such is notoriously difficult to etch. Here, an HBr-based chemistry was demonstrated for the first time to make highly selective etching of SiC at high etch rates. Nitrogen was incorporated from an NH3 gas source, resulting in high conductivity films. Residual strain and strain gradient were shown to depend on deposition parameters, and can be made negative or positive. The tribology of poly-SiC was also investigated. Much improved release stiction and in-use stiction performance relative to polysilicon MEMS was found. Furthermore, wear of poly-SiC-coated MEMS was much reduced relative to uncoated polysilicon MEMS. A prototype baseline process flow now exists to produce poly-SiC in the Berkeley Sensor and Actuator (BSAC) facility. In the second project, galvanic deposition of metals onto polysilicon surfaces has been developed. The possible applications include reflective and optical coatings for optical MEMS, microswitches and microrelays for radio frequency MEMS and catalytic surfaces for microchemical reactors. In contrast to electroless deposition, galvanic displacement deposition requires no prior activation of the surface and is truly selective to silicon surfaces. This approach was used to deposit copper, gold and rhodium onto polysilicon MEMS. A method to study the adhesion of these metals to polysilicon was developed. It was also shown that the surfaces could be rendered hydrophobic by applying thiol-based self-assembled monolayers. This procedure also lowered their surface energy to {approx}3 {micro}J/m{sup 2}, consistent with monolayer-coated polysilicon MEMS.

Si nanowires as cores were prepared using electroless metal deposition, which can be understood on the basis of the self-assembled localized microscopic electrochemical cell model. To give direct experimental proof for the formation of Si nanowires sheathed with thin DLC films, we conducted TEM on the samples. The results show that the composite Si nanowire structure has a crystalline core and a surrounding amorphous layer. Room-temperature visible photoluminescence (PL) was also observed from the as-prepared composite nanostructures.

This paper represents the electrical and optical characteristics of a SiNW/ZnO heterojunction diode and subsequent studies on the photodetection properties of the diode in the ultraviolet (UV) wavelength region. In this work, silicon nanowire arrays were prepared on p-type (100)-oriented Si substrate by an electroless metal deposition and etching method with the help of ultrasonication. After that, catalyst-free deposition of zinc oxide (ZnO) nanowires on a silicon nanowire (SiNW) array substrate was done by utilizing a simple and cost-effective thermal evaporation technique without using a buffer layer. The SEM and XRD techniques are used to show the quality of the as-grown ZnO nanowire film. The junction properties of the diode are evaluated by measuring current—voltage and capacitance—voltage characteristics. The diode has a well-defined rectifying behavior with a rectification ratio of 190 at ±2 V, turn-on voltage of 0.5 V, and barrier height is 0.727 eV at room temperature under dark conditions. The photodetection parameters of the diode are investigated in the bias voltage range of ±2 V. The diode shows responsivity of 0.8 A/W at a bias voltage of 2 V under UV illumination (wavelength = 365 nm). The characteristics of the device indicate that it can be used for UV detection applications in nano-optoelectronic and photonic devices.

'Invited'Starting from critical dimensions below 10 nm, the continuation of CMOS scaling requires the Cu replacement as an IC interconnect material by a barrierless metal with lower resistivity and better electromigration performance than Cu, such as Co and Ru. In addition, narrow dimensions of interconnect features require implementation of bottom-up metal fill schemes to mitigate defects in metal structures. At the same time, significant technological improvements are required to mitigate the pattern overlays and litho-based edge placement errors when forming multilevel structures with a half-pitch at or below 10 nm. The transition from standard multiple litho-etch deposition schemes to bottom-up area-selective deposition (ASD) is a very promising way to enable self-alignment of multilevel structures. The approaches to achieve ASD can be classified in three categories: i) intrinsic selectivity, ii) selectivity enabled by passivation of the “non-growth area” and iii) selectivity enabled by activation of the “growth area”. Among selective deposition processes, electroless deposition (ELD) and atomic layer deposition (ALD) can be effectively used due to their chemical nature and surface sensitivity. This work explores all three categories of ASD approaches for BEOL technology application, utilizing the above listed techniques for Co and Ru deposition.Intrinsically selective metal deposition can be realized for very limited number of material combinations used in IC manufacturing. Part of this work focuses on various H-based plasma treatments, which allow forming appropriate surface functionalities enabling ASD. Among various material combinations, the focus was set on amorphous carbon (a-C) as “non-growth” surface and Si-based materials, such as SiCN, as “growth” surface. An interaction of various compounds of H-based plasma, namely: H ions and H radicals with a-C was investigated experimentally. In order to support experimental observations, molecular dynamic modeling of a-C interaction with H plasma was performed, which allowed to understand the mechanisms of a-C chemical modification by H ions and radicals. Effectivity of H plasma treatment on ALD selectivity was studied for the case of selective Ru ALD using (ethylbenzyl)(1-ethyl-1,4-cyclohexadienyl)Ru(0) (EBECHRu) precursor with O2 co-reactant. In addition, an initial study of Ru ASD integration into patterned structures of technological relevant dimensions was performed.Direct implementation of intrinsically selective processes into production is a rare case in microelectronic technology. In most of the cases, however, blocking layers can be used. This work explores self-assembled monolayers (SAMs) as blocking layers for ALD. Screening of various siloxane-SAM precursors was performed to study the impact of SAM’s functional group, length of alkyl chain and deposition conditions on surface density of SAM molecules and, specifically, passivation properties of SAM against Ru ALD. An additional study was performed in order to analyze modification of (3-trimethoxysilylpropyl)diethylenetriamine (DETA)-derived SAM under ALD conditions (250 °C and O2 co-reactant). In-situ XPS as well as molecular-dynamic modelling were employed to investigate the mechanisms of DETA modification. Lastly, a removal of DETA-derived SAM from Cu “growth area” selectively with respect to SiO2 “non-growth area” using acetic acid was investigated to mitigate defectivity.Further, surface functionalization by SAMs can also be used to form appropriate surface terminal groups for further attachment of a metal catalyst or metal seed, used in subsequent selective ELD deposition. ELD is based on redox reactions on the metal substrate; therefore, it can be used for intrinsically selective metal deposition on metal substrates or metal seeds. SAMs-enabled selectivity can be used for metal growth on a dielectric surface selectively with respect to another type of the dielectric material. In the case of ELD bottom-up growth in a trench, the metal catalyst should be selectively deposited at the trench bottom dielectric layer. In this work, the selectivity of Pd metal catalyst promoted by selective surface functionalization by SAMs was investigated. It has been shown that SAMs with amino functional groups form covalent bonds with Pd catalyst, which is commonly used as a seed for subsequent ELD of various metals including Co on the Pd seed. Since the electrical properties of interconnect material are of crucial importance, an additional study of ELD Co resistivity was performed, including in-depth analysis of Co recrystallization revealing Co grain size dependency on the film resistivity.In conclusion, area-selective metal deposition processes are an important part of future microelectronic technology. This work explores ASD of Ru and Co, as the most promising Cu replacement metals. For the deposition of these metals, surface sensitive techniques are used, namely ALD and ELD. For the cases, where intrinsic selectively of the deposition technique cannot be realized for the combination of materials used in the process flow, SAM-based passivation and SAM-based activation layers were investigated.

A new method for fabricating high density printed circuit boards has been investigated. The procedure used for photoselective metal deposition on the substrate consists of five steps: adhesion treatment, sensitization, nucleation, fog inhibition and electroless metal deposition. An adhesive coated substrate was sensitized by introducing an aqueous solution containig anthraquinone sulfonic acid sodium salts, reducible noble metal salts and alcohol. The sensitized substrate was then exposed through a mask to a u.v. light. The noble metal nuclei produced by exposure were developed by electroless copper deposition after rinsing with aqueous solutions containing complex agents. Electrically‐conductive patterns thus obtained can be further intensified by second electroless plate making.

3D integration is an emerging semiconductor technology that is used to form highly integrated small-factor electronic systems by vertically stacking two or more thin electronic chips in a single package. In metallization of 3D through-substrate vias (TSuV) such as through-silicon (TSV), through-glass (TGV), through-ceramic (TCV) interconnects et al, TSuV having a very small diameter (down to several microns) and long length (hundreds of microns) are filled with plated metal in order to create massive networks of uniform interconnects with high aspect ratio (length/diameter) > 20. Existing conventional industry processes are based on expensive physical-vapor-deposition (PVD) technology, which has serious limitations on via fill uniformity and metal quality (poor step coverage, voids and other defects) as well as is limited to aspect ratios < 10.Electrochemical deposition processes have been extensively studied for 3D interconnects. These processes are appealing due to superior performance as compared to conventional PVD processes at a substantially lower cost. NANO3D’s processes are based on novel electrochemical nanomaterials (plating solutions with self-assembled suppression-based organic additives to achieve bottom up fill and conformal electroless nickel alloys/copper barrier/seed) that provide defect-free TSuV fill with Cu or other metals for aspect ratios up to >20 [1-5]. Electrochemical deposition techniques have no limitations on chips design rules (down below 20 nm) and can be applied to all types of 3D applications from logic and memory to MEMS, wireless and power electronics. Electrochemical TSuV metallization is fully compatible with all process steps in various 3D TSuV manufacturing schemes currently under evaluation and can be easily incorporated into any finally standardized “process flow of reference”. The low cost electrochemical TSuV technology addresses the major threats for adoption of 3D TSuV that is the scalability to high aspect ratio and the cost. Another threat for adoption of 3D TSuV technology, that is related to power density limitation and thermal dissipation from thinned dies are expected to be solved by controlled expansion metal alloys (INVAR et al.) where electrochemical deposition offers high flexibility for designers with various aspect ratios and via sizes.In this work, copper and INVAR electroplating as well as nickel alloys and copper electroless deposition processes have been developed and characterized to achieve bottom up fill in trenches & vias of high aspect ratio and wide range of features sizes with superior interconnect properties including low electrical resistivity, CTE and internal stress. Plated films with low-thermal expansion (of about 0.4±0.1 (x10-6, (K-1)) and ultralow internal stress (of about 30 MPa) have been deposited on patterned substrates such as TSuV on various substrates, redistribution layers (RDL), pillars and bumps for 3D Interconnects. The plated patterned substrates are flat, smooth, uniform, defect free and possess with complete fill of TSuV and well controlled thickness non-uniformity of about 5 % @ 3 σ for Cu & INVAR & Ni alloys films (Figure). Thermal shock testing of plated TSuV substrates showed promising reliability & adhesion results after 500 cycles of thermal shock with no cracking and delamination. References V.M. Dubin, A.L. Gindilis, B.L. Walton, K. Norelli, A.U. Liyanage, S.R. Bauers and D.C. Johnson. ECS Transactions, 2017, 75 (34), 27.S. Taushanoff and V. M. Dubin. ECS Transactions, 2017, 77 (11), 877.V.M. Dubin, K. Norelli, and P.N. Plassmeyer. ECS Transactions, 2017, 77 (11), 887.V.M. Dubin, M.O. Lisunova, and B.L. Walton. Journal of The Electrochemical Society, 2017, 164, D321.S. Taushanoff, V.M. Dubin, A. Wallace and H. A. Mantooth. ECS Transactions, 2018, 85 (13) 803. Figure 1

Self-organized synthesis of micrometer scale silver disks by electroless metal deposition on Si-incorporated diamond-like carbon films

Three-dimensional (3D) integration is an emerging technology that vertically interconnects stacked dies of electronics and/or MEMS-based transducers using through silicon vias (TSVs). TSVs enable the realization of devices with shorter signal lengths, smaller packages and lower parasitic capacitances, which can result in higher performance and lower costs of the system. In this paper we demonstrate a new manufacturing technology for high-aspect ratio (>;8) through silicon metal vias using magnetic self-assembly of gold-coated nickel rods inside etched through-silicon-via holes. The presented TSV fabrication technique enables through-wafer vias with high aspect ratios and superior electrical characteristics. This technique eliminates common issues in TSV fabrication using conventional approaches, such as the metal deposition and via insulation and hence it has the potential to reduce significantly the production costs of high-aspect ratio state-of-the-art TSVs for e.g. interposer, MEMS and RF applications.