A new quantization algorithm for fir filters coefficients

As Field programmable Gate Array (FPGA) technology has steadily improved, FPGAs are now viable alternatives to other technology implementations for high-speed classes of digital signal processing (DSP) applications. In particular, radar front-end signal processing, an application formerly dominated by custom very large scale integration (VLSI) chips, may now be a prime candidate for migration to FPCA technology. As this paper demonstrates, current FPGA devices have the power and capacity to implement a FIR filter with the performance and specifications of an existing, in-system, front-end signal processing custom VLSI chip. A 512-tap, 18-bit FIR filter was built that could achieve sample rates of 5 MHz (with a clock rate of at least 40 MHz) using Xilinx Virtex FPGA technology, and was demonstrated through simulation. Distributed arithmetic was determined to be the most optimal structure for a FPGA FIR design, although future research may show that fast FIR algorithms or filtering in the frequency domain might give better results.

FIR stands for Finite Impulse Response which act as signal conditioners for digital signal processor. It takes an input signal, limits the frequencies to a desired frequency range and giving the output as the subtraction of the original signal to the desired limited frequencies. The FIR filters play a vital role in wide range of DSP applications like speech processing, data compression, signal processing, image processing etc. where the noise cancellation and redundant sound cancellation is required for achieving a desired signal. So we design a FIR filter which gives better performance with less power consumption considering the resources. Implementing the design of FIR filter using (Multiplier and Accumulation Control Unit)MAC where MAC unit gives the fundamental concept of the neural networks. The proposed design gives a improved performance while in comparison with the conventional FIR filter. FIR filter is synthesized and implemented in Xilinx FPGA environment using Xilinx ISE platform evaluating the performance in terms of LUT's, FF's & power. Therefore concluding with the lower power consumption of the proposed FIR filter than conventional FIR filter.

An optimization approach to the design of frequency sampling filters implemented with finite word length architectures

Interrelations between the coefficients of FIR digital differentiators and other FIR filters and a versatile multifunction configuration

The Reconfigurable FIR filters are commonly used digital filters which find its major applications in digital signal processing and multi-standard wireless communications. The Direct form of FIR filter used in DSP application which consumes more area and power. To overcome this problem Multiplier Control Signal Decision (MCSD) window schemes is incorporated into direct form FIR filter in order to dynamically change the filter order. Conventional reconfigurable FIR filter is designed using Russian Peasant Multiplier which consumes more area and delay due to poor performance of adder used in multiplication unit. In this study, modified reconfigurable FIR filter is designed to further reduce the area, power and time. In proposed Reconfigurable FIR filter, a Wallace adder is replaced by carry select adder with sklansky adder in Russian Peasant Multiplication technique. Hence, modified Reconfigurable FIR filter with carry select adder with sklansky adder consumes less area, delay and power than the conventional Reconfigurable FIR architecture with Russian Peasant Multiplication technique.

The availability of fast, general‐purpose laboratory computers has dramatically changed the way research is done in many areas of psychoacoustics. In studies of sound localization, for example, standard digital signal‐processing techniques are used to synthesize stimuli for headphone presentation that contain all of the localization cues (e.g., interaural differences, pinna effects) that are available from sounds presented in free field. This brings to localization research a much needed degree of stimulus control and specificity, and allows us to address certain basic issues that were heretofore inaccessible. This presentation will survey the general principles involved in the application of digital signal processing to localization research, and will discuss the practical limitations of the specific techniques that are used (e.g., FFTs, FIR filters, inverse filtering). Empirical data will be shown in order to address questions relating to the classic tradeoffs among signal/noise ratio, bandwidth, word‐length, and sampling frequency. The feasibility of real‐time digital processing in currently available PC‐based systems will also be discussed. [Work supported by NIH, NSF, and NASA.]

This paper proposes a weighted least-squares (WLS) method for designing variable one-dimensional (1-D) FIR digital filters with simultaneously variable magnitude and variable non-integer phase-delay responses. First, the coefficients of a variable FIR filter are represented as the two-dimensional (2-D) polynomials of a pair of spectral parameters; one is for tuning the magnitude response, and the other is for varying its non-integer phase-delay response. Then the optimal coefficients of the 2-D polynomials are found by minimizing the total weighted squared error of the variable frequency response. Finally, it is shown that the resulting variable FIR filter can be implemented in a parallel form, which is suitable for high-speed signal processing.

Low energy, long sustainable and high-speed FIR filter based on truncated multiplier with SCG-HSCG adder

A method is presented for designing optimal adaptive digital filters. The derivation is based upon filtering a desired signal which has been corrupted by a "noise" like signal so the least-square error between the filtered output and the desired output is minimized. The filter is contrasted with both the Levinson and Widrow filters. The greatest utility of the derived filters are in digital signal processing applications where real-time or stability are critical constraints.

Power and delay efficient fir filter design using ESSA and VL-CSKA based booth multiplier

Finite Impulse Response (FIR) Filter occupied a significant position in most of Digital Signal Processing (DSP) Applications. The behaviour of FIR filters can be realized in software for DSP applications and executed on Digital Signal Processor architectures. These kinds of digital filters consider digital components, digital input and perform mathematical computations to produce digital output. In modern DSP applications demanding area efficient architecture for DSP algorithms while optimizing throughput. This can be achieved by design of hardware architectures for DSP algorithms and apply design optimization techniques to accelerate the throughput and minimize area. This article attempts to develop hardware architectures for FIR Filter and apply the design optimization techniques present in literature. In this article, High Level Synthesis concepts were adapted to develop hardware architecture for FIR filter and optimization techniques have been applied to optimize design attributes like area, throughput and power. Finally, design attributes are summarized after applying optimization techniques and published significant architectural attributes suitable for real life DSP applications.

In this paper, it is tried to transfer one of the powerful tools for image processing from the frequency domain to spatial domain. In which the frequency concepts is used in the field of image processing based on FPGA. The process is as follows that first a low-pass FIR filter in frequency domain is designed and then it is transferred from frequency domain to spatial domain and implemented as an IP Core standard structure in FPGA. The implemented IP CORE structure is streaming and the input and output images of type gray. Because the use of array and high-frequency processing in FPGA, it has wide applications in image processing field, especially for highspeed image processing. Finally, the implementation of 2D FIR filter and eyewitness in VGA's output and the comparison between the actual image and filtered image, it is obvious that high-frequency changes are decreased in the image.

Based on fast convolution algorithm, this paper proposes improved parallel FIR filter structures for linear-phase FIR filters where the number of taps is a multiple of parallelism. The proposed parallel FIR structures not only use fast convolution algorithm to reduce the number of subfilter, but also exploit the symmetric (or antisymmetric) coefficients of linear-phase FIR filter to reduce half the number of multiplications in subfilter section at the expense of additional adders in preprocessing and postprocessing blocks. The proposed parallel FIR structures save a large amount of hardware cost for symmetric (or antisymmetric) coefficients from the reported FFA parallel FIR filter structures, especially when the length of the filter is large, e.g., the proposed 4-parallel FIR filter structure has eight subfilter blocks in total and four subfilter blocks contain symmetric coefficients, whereas the improved FFA structure has nine subfilter blocks in total and four contain symmetric coefficients. Specifically, for a 4-parallel 576-tap filter, the proposed design saves 144 multipliers (14.3%), 135 adders (10.2%) and 143 delay elements (11.1%).

Signal processing has always been a critical aspect of interferometric spectroscopy. The main value of Fourier Transform Spectroscopy (FTS) is to provide the maximum information per unit time. This means that careful signal processing is required to maximize the signal to noise ratio of the result. Digital signal processing (DSP) is not new in FTS. DSP for apodization, Fourier transform, phase correction, and some digital filtering have been used for many years. The first difficulty encountered in using DSP is the required transformation of the continuous time signal to a sequence of finite precision numbers, that is a discrete time, discrete magnitude representation of the continuous signal. Today, sampling and digitization with conventional techniques are reasonably straightforward, with digitization noise of the order of 2−16. Advances in several aspects of FTS technology, including step scanning, have created the need to lower the digitization noise. The processing of signals from multiple modulation FTS experiments, specially step-scan signals, has presented serious limitations until recently, due primarily to the performance restrictions of the available hardware, and the fundamental limitations of the analog systems used. The application of DSP techniques to reduce the sampling and digitization errors are reviewed, and practical solutions that can provide digitization noise lower than 2−24 with low cost systems are described. Some of the causes and effects of sampling error are reviewed, to clarify common misunderstandings. DSP applications in the detection of multiple modulation step-scan experiments and photoacoustic spectroscopy are described in detail. These applications allow the measurement of the signal during the entire step time, eliminate interference of secondary effects of phase modulation, and integrate the entire experiment in the data system, eliminating all the analog adjustments (knobs) needed when lock-in amplifiers are used.

This paper introduces robust stability techniques for the computation of exact bounds for the frequency response of FIR and IIR digital filters in which the l/sup /spl infin// norm of the coefficients is bounded. >