A New Scheme to Reduce Leakage in DeepSubmicron Cache Memories with No Extra Dynamic Consumption

Sex dependent mechanical properties of the human mandibular condyle

In this paper analysis of noise margin and power dissipation of a novel low power proposed 8T SRAM cell has been reported. In the proposed structure two voltage sources are connected with the Bit line and the other connected with the Bit bar line are used in order to reduce voltage swings at the output nodes of bit and bit bar line during the write operation. Static noise margin values have been calculated at different transistor cell ratios and different transistor pull-up ratios. Similarly the power dissipations at different supply voltages, temperatures and bit line capacitances are calculated. Results of static noise margin and power dissipations are compared to those of conventional 6T and 11T SRAM cells. The proposed SRAM cell has better stability at different cell ratios and pull-up ratios in comparison to 6T and 11T SRAM cells. Power dissipation in the proposed SRAM cell is less at different supply voltages, temperatures and bit line capacitances in comparison to 6T and 11T SRAM cells. The simulation has been done in 350nm CMOS environment by using BSim4 model. Microwind 3.1 is used for schematic design.

In this paper, we propose Joint SRAM (JSRAM) cell, a novel circuit-level hardening solution for having a flexible trade-off between cache capacity and reliability. Our solution aims at addressing both permanent and transient faults in SRAM cells. JSRAM technique enhances read-stability by increasing critical Read Static Noise Margin (RSNM) to decrease faults when circuit operates at lower VDD voltages, while improving yield. It also increases hold-stability to mitigate against soft-errors, due to noise or radiation when circuit works in harsh environmental conditions. Moreover, our approach is resistant to Multi Bit Upsets (MBUs) while it is fully immune against single faults due to a novel self-correcting technique. Specifically in fault prone condition, some user pre-selected cache lines and ways are combined together vertically and horizontally at circuit level to form more robust cache cells. Four cells are joined by joiner circuits to form one robust cell. Joining cells can be selected far enough to cope with MBUs. In the case of soft-errors, this technique can be interpreted as virtually doubling transistor size. In the case of permanent faults, it can be seen as increasing β ratio to improve readability. This approach provides versatile and flexible solution with negligible performance penalty and low area overhead. This technique requires one extra transistor per cell for joiner circuit. However, extra transistor is only involved in the reliable mode. Therefore it can be described as 6T+1T SRAM cell. While our implementation is on 6T SRAM with 22nm technology, it is applicable to other SRAM structures and technologies.

Half-select disturb-free single-ended 9-transistor SRAM cell with bit-interleaving scheme in TMDFET technology

In this paper, a new asymmetric 6T (AS6T) SRAM cell is presented in a standard 90-nm CMOS technology employing separate bitline and wordline for read operation. Utilizing separate bitline and wordline during read operation decouples the other cell node from the bitline, hence, enhancing the read static noise margin (SNM) by almost 2 times as compared to the conventional 6T SRAM. The read SNM of 6T and AS6T SRAM cells during a read operation in 1.0 V supply is 85 mV and 159 mV, respectively. The mean μ of the hold SNM for both cells are well above 140 mV, however, the μ of the conventional 6T SRAM is larger than that of AS6T cell. The impact of process parameter variations on read and hold noise margin of the asymmetric 6T cell and the conventional 6T cell, considering various supply voltages, is investigated. The results demonstrate yield improvement, up to 99.5%, and indicate that the supply voltage can scale down to 0.45 V.

SummaryThe conventional 8T SRAM cell with isolated read port is suggested as an alternative to overcome the read‐write conflicts associated with 6T SRAM cell. However, in near threshold and sub‐threshold regions, 8T cell performance is limited by reduced ION/IOFF ratio, deteriorated RBL voltage swing, data dependency, and higher read failures, although the existing SRAM cells address some of these issues but still suffer from degraded performance due to the trade‐off between leakage and read currents. In this paper, a 9T SRAM cell with novel read port is proposed that aims for low and data‐independent leakages, high ION/IOFF ratio, and large RBL voltage swing in near threshold and sub‐threshold regions. The performance of the proposed cell is compared with 7T, 8T, 9T, and 10T cells at 32 nm technology node by simulating a column of 128 cells to demonstrate its versatility over others. The proposed cell shows enhanced ION/IOFF ratio (71.2X), large RBL voltage swing and data‐independent leakages at VDD = 0.3 V in comparison to the conventional 8T SRAM cell. The results at different PVT corners are also captured to validate the impeccable performance of the proposed cell irrespective of operating conditions.

This paper presents a FinFET based 6T SRAM cell, with separate read access path and write path, designed by combining the advantages of conventional single ended 5T and the conventional 8T SRAM cells. The proposed SRAM cell achieves 70% and 55% of write performance improvement in terms of Power delay product (PDP) than 8T (also conventional 6T) and 5T SRAM cells respectively. Proposed cell achieves 78% of hold 1 and 40% of hold 0 static power reduction than the conventional 5T, 6T and 8T cells. The proposed cell is read SNM free and also achieves better hold SNM and write ability than 5T and 8T SRAM cells.

This paper presents the design and evaluation of a new SRAM cell made of nine transistors (9T). The proposed 9T cell utilizes a scheme with separate read and write wordlines; it is shown that the 9T cell achieves improvements in power dissipation, performance and stability compared with previous designs (that require 10T and 8T) for low-power operation. The 9T scheme is amenable to small feature sizes as encountered in the deep sub-micron/nano ranges of CMOS technology.

Read stability issue is becoming more and more concerned in accordance with rapid development of CMOS IC fabrication technology. A new nine transistor (9T) SRAM cell with enhanced stability during a read operation and reduced power consumption is proposed recently. To put it into practical an SRAM based on it needs to be built. This paper designs three peripheral circuits that are needed in the building process, including row-selecting circuit suitable for the dual control signal character of 9T SRAM cell, simplified writing circuit that can effectively pull down the bit-lines and choose which to pull with only three N-type transistors and power-reduced sense amplifier with its switch transistor controlled by the logic `and' result of one external and two internal signals that can shut down the circuit when there is enough voltage difference between outputs. The active power consumption of the sense amplifier with and-gate is 38% lower than the one without it. An 8-kb SRAM based on 9T cell using peripheral circuits proposed in this paper is built, and the correctness of the simulation result of its functionality shows that SRAM based on 9T cell can work well with proposed peripheral circuits.

Presented in this paper are: 1) information-theoretic lower bounds on energy consumption of noisy digital gates and 2) the concept of noise tolerance via coding for achieving energy efficiency in the presence of noise. In particular, lower bounds on a) circuit speed f/sub c/ and supply voltage V/sub dd/; b) transition activity t in presence of noise; c) dynamic energy dissipation; and d) total (dynamic and static) energy dissipation are derived. A surprising result is that in a scenario where dynamic component of power dissipation dominates, the supply voltage for minimum energy operation (V/sub dd, opt/) is greater than the minimum supply voltage (V/sub dd, min/)for reliable operation. We then propose noise tolerance via coding to approach the lower bounds on energy dissipation. We show that the lower bounds on energy for an off-chip I/O signaling example are a factor of 24/spl times/ below present day systems. A very simple Hamming code can reduce the energy consumption by a factor of 3/spl times/, while Reed-Muller (RM) codes give a 4/spl times/ reduction in energy dissipation.

Leakage current consumes the majority of the active mode energy in the high-performance integrated circuits of today. In particular, in high microprocessor and system-on-chip architectures, the SRAM cell array is the primary source of leakage current. So low-leakage SRAM design is essential. Today’s VLSI designs are all about cutting down on power dissipation, supply voltage, leakage currents, and chip area. However, raising these parameters increases sub-threshold leakage currents and power dissipation, reducing design performance. Increasing the cell area reduces leakage power dissipation in standby mode. To solve these problems, it is best to cut down on effective leakage currents and dynamic power dissipation. For low voltage and energy constraints, the power dissipation, area, and delay performance of the low-power design of the 6T-SRAM cell with the DTMOS technique for a proposed low-power SRAM will be implemented in the Tanner EDA tool in 22 nm technology. The power of both types of SRAM cells will be compared using low-power techniques and a power analysis.

Microprocessor performance has been improved by increasing the capacity of on-chip caches. However, the performance gain comes at the price of increased static energy consumption due to sub-threshold leakage current. This paper compares three techniques for reducing static energy consumption in on-chip level-1 and level-2 caches. One technique employs low-leakage transistors in the memory cell. Another technique, power supply switching can be used to turn off the memory cells and discard their contents. A third alternative is dynamic threshold modulation, which places the memory cells in a standby state that preserves cell contents. In our experiments, we explore the energy/performance trade-offs of these techniques and find that the dynamic threshold modulation achieves the best results for level-1 caches, improving the energy-delay product by 2% in a level-1 instruction cache and 7% in a level-1 data cache. Low-leakage transistors perform best for the level-2 cache as they reduce the static energy by up to 98% and improve the energy-delay product by more than a factor of 50.

본 논문에서는 Carbon/Epoxy 복합재 적층판에 대하여 실사격 실험을 수행하였으며, 복합재 적층판의 흡수에너지를 예측하기 위한 개선된 방법을 제시하였다. 고속충격실험 과정에서 충격체의 질량손실을 고속카메라를 통하여 거시적으로 확인하였으며, 따라서 이를 고려하여 복합재 적층판의 흡수에너지를 계산하였다. 고속충격을 받는 복합재 적층판의 흡수에너지를 예측하기 위한 모델을 제시하였으며, 복합재 적층판의 흡수에너지는 크게 정적에너지와 동적에너지로 분류하였다. 정적에너지 계산은 섬유의 파손과 정적 탄성에너지와 관련 있는 준정적 관통실험식을 통해 구한 관통에너지를 사용하였다. 동적에너지는 변형되는 시편의 운동에너지와 손실된 파편 질량들의 운동에너지로 나뉠 수 있다. 최종적으로 충격체 질량손실을 고려하여 예측된 흡수에너지와 실험결과를 비교/분석하였다. In this paper, we conducted high velocity impact test for Carbon/Epoxy composite laminates and proposed advanced method for predicting the absorbed energy of composite laminates. During high-velocity impact test, we discovered loss of projectile mass macroscopically using high speed camera, thus we calculated the absorbed energy of composite laminates by taking loss of projectile mass into account. We proposed a model for predicting the absorbed energy of composite laminates subjected to high-velocity impact, the absorbed energy was classified into static energy and dynamic energy. The static energy was calculated by the quasi-static perforation equation that is related to the fiber breakage and static elastic energy. The dynamic energy can be divided by the kinetic energy of deformed specimen and fragment mass. Finally, the predicted absorbed energy considering loss of projectile mass was compared with experimental results.

Implantable cardiac devices have very strict restrictions on energy dissipation since battery change requires surgery. Today the battery longevity of pacemakers during standard use is up to 10 years which might seem sufficient. However, new functionality is constantly being introduced requiring more advanced signal processing algorithms which in turn increase energy dissipation. New battery technologies are of course beneficial, but compared to the progress of electronics according to Moore's Law, battery development is very slow and energy issues have to be solved by more efficient implementations. Technology scaling will help us by reducing capacitance and thereby lowering the dynamic energy. However, for technology nodes of 130 nm and below static energy dissipation due to leakage currents, which traditionally could be ignored, are becoming increasingly important. This is especially true for low sampling rate applications were the dynamic energy often may be ignored. In this paper we will make an introduction to the topic, discuss the mechanisms of energy dissipation and present some specific solutions regarding implementation of signal processing in implantable cardiac devices. Special attention will be given to reduced leakage and a dual mode operation.

This paper presents a forward body-biasing (FBB) technique for active and standby leakage power reduction in cache memories. Unlike previous low-leakage SRAM approaches, we include device level optimization into the design. We utilize super high Vt (threshold voltage) devices to suppress the cache leakage power, while dynamically FBB only the selected SRAM cells for fast operation. In order to build a super high Vt device, the two-dimensional (2-D) halo doping profile was optimized considering various nanoscale leakage mechanisms. The transition latency and energy overhead associated with FBB was minimized by waking up the SRAM cells ahead of the access and exploiting the general cache access pattern. The combined device-circuit-architecture level techniques offer 64% total leakage reduction and 7.3% improvement in bit line delay compared to a previous state-of-the-art low-leakage SRAM technique. Static noise margin of the proposed SRAM cell is comparable to conventional SRAM cells.