A novel clustered multi-dictionary code compression method

Chapter 11 - The ARM Architecture

CPU contains the most critical technology of computer. At present, popular processors use not only X86 instruction set such as Intel and AMD, but also MIPS instruction set such as Loongson, Alpha instruction set such as Shenwei, and ARM instruction set such as Phytium. Aiming at the requirement of high performance computing and high bandwidth communication, a high performance server used four channel S2500 processors is proposed based on CC-NUMA parallel processing architecture. In the present paper, the characteristics of S2500 processor are analyzed, the typical operation mode of instruction pipeline is studied, and the topology of 4 way S2500 processors is proposed. While the parallel computing performance of the system is improved, TOE technology is applied to the system in order to minimize the occupancy of CPU resources in full-load communication of 10G Ethernet interface. By the test of comparing the computing performance of single processor and four channel processors, and the CPU occupancy rate of common network card and TOE network card, the results show that the server can achieve efficient parallel computing capability by using CC-NUMA architecture and 4 way S2500 processors. The TOE chip can guarantee 10G Ethernet communication capability while occupying CPU resources as little as possible. The designed system is suitable for application scenarios of high performance computing and high communication bandwidth.

Most dynamic binary translators (DBT) and optimizers (DBO) target binary traces, i.e. frequently executed paths, as code regions to be translated and optimized. Code region formation is the most important first step in all DBTs and DBOs. The quality of the dynamically formed code regions determines the extent and the types of optimization opportunities that can be exposed to DBTs and DBOs, and thus, determines the ultimate quality of the final optimized code. The Next-Executing-Tail (NET) trace formation method used in HP Dynamo is an early example of such techniques. Many existing trace formation schemes are variants of NET. They work very well for most binary traces, but they also suffer a major problem: the formed traces may contain a large number of early exits that could be branched out during the execution. If this happens frequently, the program execution will spend more time in the slow binary interpreter or in the unoptimized code regions than in the optimized traces in code cache. The benefit of the trace optimization is thus lost. Traces/regions with frequently taken early-exits are called delinquent traces/regions. Our empirical study shows that at least 8 of the 12 SPEC CPU2006 integer benchmarks have delinquent traces. In this paper, we propose a light-weight region formation technique called Early-Exit Guided Region Formation (EEG) to improve the quality of the formed traces/regions. It iteratively identifies and merges delinquent regions into larger code regions. We have implemented our EEG algorithm in two LLVM-based multi-threaded DBTs targeting ARM and IA32 instruction set architecture (ISA), respectively. Using SPEC CPU2006 benchmark suite with reference inputs, our results show that compared to an NET-variant currently used in QEMU, a state-of-the-art retargetable DBT, EEG can achieve a significant performance improvement of up to 72% (27% on average), and to 49% (23% on average) for IA32 and ARM, respectively.

Most dynamic binary translators (DBT) and optimizers (DBO) target binary traces, i.e. frequently executed paths, as code regions to be translated and optimized. Code region formation is the most important first step in all DBTs and DBOs. The quality of the dynamically formed code regions determines the extent and the types of optimization opportunities that can be exposed to DBTs and DBOs, and thus, determines the ultimate quality of the final optimized code. The Next-Executing-Tail (NET) trace formation method used in HP Dynamo is an early example of such techniques. Many existing trace formation schemes are variants of NET. They work very well for most binary traces, but they also suffer a major problem: the formed traces may contain a large number of early exits that could be branched out during the execution. If this happens frequently, the program execution will spend more time in the slow binary interpreter or in the unoptimized code regions than in the optimized traces in code cache. The benefit of the trace optimization is thus lost. Traces/regions with frequently taken early-exits are called delinquent traces/regions. Our empirical study shows that at least 8 of the 12 SPEC CPU2006 integer benchmarks have delinquent traces.

A novel clustered multi-dictionary code compression method is proposed to effectively reduce the memory size which program code stored. According to the repeat times of distinct codes, the code set is clustered into several clusters. Each cluster is compressed with different dictionary and the codeword length is the same for the same dictionary. Shorter codeword is used for the dictionary whose size is smaller. Experimental results of MiBench benchmark compiled for ARM and MIPS show that the compression efficiency of this method is superior to the traditional multi-level dictionary-based code compression. The latency of instruction fetch is almost not increased, decode logic overhead is tiny and acceptable. Furthermore, the storage-bandwidth is increased.

In embedded system design, memory is one of the most restricted resources, posing serious constraints on program size. Code compression has been used as a solution to reduce the code size for embedded systems. Lossless data compression techniques are used to compress instructions, which are then decompressed on-the-fly during execution. Previous work used fixed-to-variable coding algorithms that translate fixed-length bit sequences into variable-length bit sequences. In this paper, we present a class of code compression techniques called variable-to-fixed code compression (V2FCC), which uses variable-to-fixed coding schemes based on either Tunstall coding or arithmetic coding. Though the techniques are suitable for both reduced instruction set computer (RISC) and very long instruction word (VLIW) architectures, they favor VLIW architectures which require a high-bandwidth instruction prefetch mechanism to supply multiple operations per cycle, and fast decompression is critical to overcome the communication bottleneck between memory and CPU. Experimental results for a VLIW embedded processor TMS320C6x show that the compression ratios using memoryless V2FCC and Markov V2FCC are around 82.5% and 70%, respectively. Decompression unit designs for memoryless V2FCC and Markov V2FCC are implemented in TSMC 0.25-/spl mu/m technology.

Time series compression encodes the information in a time-ordered sequence of data points into fewer bits, thereby reducing storage costs and possibly other costs. Compression methods are either general or XOR-based. General compression methods are time-consuming and are not suitable in streaming scenarios, while XOR-based methods are unable to consistently maintain high compression ratios. Further, existing methods compress the integer and decimal parts of floating-point values as a whole, thus disregarding the different characteristics of the two parts. We propose Camel , a new compression method for floating-point time series with the goal of advancing the compression ratios and efficiency achievable. Camel compresses the integer and decimal parts of the double-precision floating-point numbers in time series separately; and instead of performing XOR operations on values using their previous value, Camel identifies values that enable higher compression ratios. Camel also includes means of indexing compressed data, thereby making it possible to query compressed data efficiently. We report on an empirical study of Camel and 11 lossless and 6 lossy compression methods on 22 public datasets and three industrial datasets from AliCloud. The study offers evidence that Camel is capable of outperforming existing methods in terms of both compression ratio and efficiency and is capable of excellent compression performance on both time series and non-time series data.

Embedded systems are constrained by the available memory. Code compression techniques address this issue by reducing the code size of application programs. Dictionary-based code compression techniques are popular because they offer both good compression ratio and fast decompression scheme. Recently proposed techniques by J. Prakash et al. (2003) improve standard dictionary-based compression by considering mismatches. This paper makes two important contributions: i) it provides a cost-benefit analysis framework for improving the compression ratio by creating more matching patterns, and ii) it develops an efficient code compression technique using bitmasks to improve the compression ratio without introducing any decompression penalty. To demonstrate the usefulness of our approach we have used applications from various domains and compiled for a wide variety of architectures. Our approach outperforms the existing dictionary-based techniques by an average of 15%, giving a compression ratio of 55% - 65%

Efficient and accurate waveform compression is essentially important for the application of analog circuit transition simulation nowadays. In this article, an analog waveform compression scheme is proposed which includes two compressed formats for representing small and large signal values, respectively. The compressed formats and the corresponding compression/decompression approaches ensure that both the absolute and relative errors of each signal value restored from the compression are within specified criteria. The formats are integrated in a block-by-block compressing procedure which facilitates a secondary lossless compression and a three-stage pipeline scheme for fast conversion from the simulator's output to the compressed hard-disk file. Theoretical analysis is presented to prove the accuracy-ensured property of our approach. Two schemes are also proposed to incorporate the prediction method. They achieve larger compression ratio for some cases while preserving the accuracy and runtime efficiency. Experiments are carried out with voltage waveforms from industrial circuits. The results validate the accuracy and the efficiency of the proposed techniques. The obtained compression ratio is 2.6X larger than existing work without overhead, even though the latter induces much larger error. Compared with the original double-precision floating number format, the proposed approach achieves the compression ratio of 26 averagely and up to 70, while keeping the relative error less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> and absolute error less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> . And with the pipelined computation, the proposed compression approach hardly increases time cost to the transient simulation.

This paper conducts a comparative analysis of the impact of unsparsing by data scaling on lossless data compression methods. The most commonly used data compression algorithms such as gzip, zlib, bzip2, and lzma are tested by their compression efficiency in unsparsed datasets by the performance metrics such as compression time, decompression time, and compression ratio for both the original and scaled datasets. Five different data scaling techniques are investigated to transform the original data into unsparsed data such as min-max, robust, absolute max, standardization, and normalization. Our research reveals relationships between data scaling methodologies and compression performance, with disparities in compression efficiency and computational complexity. Fur-thermore, we investigate the effects of scaling on compression ratio and provide results for improving the understanding of the factors that influence lossless data compression methods for non-sparse tabular data.

The trajectory data of vessel AIS (automatic identification system) has important theoretical and application value for information supporting decisions. However, large sizes lead to difficulties in storing, querying, and processing. To solve the problems of high compression ratio and longtime consumption of the existing online trajectory compression algorithm, an SPM (scan-pick-move) trajectory data compression algorithm added sliding window is proposed. In order to better compress vessel trajectory data regarding compression efficiency, the sliding window is added to the classical SPM algorithm. In order to reduce trajectory data storage space, the maximum offset distance reference trajectory point is used as the criterion of whether the current trajectory point can be compressed. In this paper, the multi-dimensional space-time characteristics of trajectory data, such as distance error, compression ratio and compression time, are selected to evaluate the trajectory compression method from three levels: geometric characteristics, motion characteristics and compression efficiency. Compared with the existing SPM trajectory data compression algorithm, parallel experiments are conducted based on AIS data gathered over the duration of a month in the Japan Osaka Bay. The SPM trajectory compression algorithm added sliding window can significantly reduce the compression time and outperforms other existing trajectory compression algorithms in term of average compression error at high compression strengths. Also, the proposed method has high compression efficiency in the range of commonly used compression thresholds.

In this article we investigate the trade-off between the compression ratio and distortion of a recently published compression technique specifically devised for multichannel electroencephalograph (EEG) signals. In our previous paper, we proved that, when singular value decomposition (SVD) is already performed for denoising or removing unwanted artifacts, it is possible to exploit the same SVD for compression purpose by achieving a compression ratio in the order of 10 and a percentage root mean square distortion in the order of 0.01 %. In this article, we successfully demonstrate how, with a negligible increase in the computational cost of the algorithm, it is possible to further improve the compression ratio by about 10 % by maintaining the same distortion level or, alternatively, to improve the compression ratio by about 50 % by still maintaining the distortion level below the 0.1 %.

The rapid growth of smart grid systems has resulted in an exponential increase in data volume. This has led to significant challenges for efficient storage and transmission, thereby necessitating the development of advanced data compression techniques. Traditional techniques often struggle to maintain a balance between compression efficiency and data integrity, particularly when dealing with diverse and large datasets. To address this issue, this paper presents an adaptive data compression algorithm based on discrete wavelet transform (DWT) and Horse Herd Optimization (HHO). The proposed technique significantly improves storage by dynamically optimizing key performance metrics, such as signal-to-noise ratio (SNR), mean square error (MSE), and compression ratio (CR). By employing a robust optimization algorithm, it effectively addresses the computational challenges of processing large-scale and real-time data. This adaptability ensures the algorithm is well-suited for dynamic smart grid environments, providing a scalable and reliable solution to modern data management demands. This technique uses HHO to find the optimal thresholding for smart grid data compression. In general, DWT-based data compression is carried out using a universal threshold for ignoring particular wavelet coefficients. But, the performance of data compression varies for different threshold values. Hence, selecting an optimal threshold is a challenging task for data compression. Therefore, to solve this issue, an effective optimization algorithm is needed. In this work, a Multi-Objective Horse Herd Optimization (MO-HHO) algorithm is proposed to find the optimal threshold. The suggested MO-HHO algorithm accurately determines the global optimum threshold. Hence, it maintains a good compromise between SNR, MSE and CR. The effectiveness of the proposed algorithm is examined using three different data sets. Various datasets from the IEEE Power quality wave data, Household Electric Power Consumption data and Real-time dataset from an experimental set-up were used to test the proposed algorithm. The outcome demonstrates that the suggested MO-HHO algorithm performs better than the other conventional methods.

Code Compression has been used to alleviate the memory requirements as well as to improve performance and/or minimize energy consumption. On the other hand, implementing security primitives on Embedded Systems is always costly in terms of area and performance. In this paper we present a code compression method, the IBC-EI (instruction based compression with encryption and integrity checking), tailored to provide integrity checking and encryption to secure processor-memory transactions. The principle is to keep the code compressed and ciphered in the memory, thus reducing the memory footprint and providing more information per memory access. For the Leon processor and a set of benchmarks from the Mediabench and MiBench suites the habitual overheads due to security trend to zero in comparison to a system without security neither compression.

Reliable transmission of high quality images through wireless communication channels represents a great challenge, especially for real-time applications. From one aspect, it is necessary to achieve efficient compression that maintains the good image quality without increasing the transmission bandwidth. Secondly, wireless channels impairments such as fading and interference increase the probability of errors when the image data is transmitted. This necessitates the use of efficient channel coding to protect against channel errors. However channel coding results in increasing the transmitted bit rate, for real time applications. Again, this is constrained by the usually limited available transmission bandwidth. In this paper, this dilemma is solved by adopting new unequal error protection techniques that are used to achieve the above requirements by using image adaptive combined compression and error protection. This is achieved through image segmentation and adaptive compression and channel coding according to the importance of the image segments. Two proposed techniques are introduced. In the first suggested technique, the image is partitioned into equal blocks and the data classification is performed in the DCT domain. The DCT coefficients of the different blocks are classified to different classes of importance and hence they are given different rates of error protection and compression ratios. The second technique is based on adaptive image segmentation using quadtree decomposition into unequal segments before applying the DCT. Finally, to improve the quality of received images, the Orientation Adaptive Sequential Interpolation error-concealment technique is applied to the reconstructed images. Computer simulation shows that the proposed techniques achieve high degree of robustness against channel impairments with good image quality with acceptable data rates.