A novel compilation approach for image processing graphs on a many-core platform with explicitly managed memory

Image processing has high computational requirements. As many papers (including [Frisk 2010; N. Zhang and Wang 2010; Yang et al. 2008]) have indicated, a number of image processing operations can be optimized by heavy parallelization of the computation. Currently, one of the best options for parallelized image processing is using general purpose computation on graphics processing units (GPGPU).In the area of GPGPU, a rather wide range of APIs is available and finding an appropriate choice for a project is challenging. In the course of being able to provide guidance on selecting the right API in an image processing context, four GPU programming models were compared according to their platform independence, usability, and performance. The four investigated APIs are CUDA, OpenCL 1.2, Vulkan, and SYCL.To gain information on the metrics usability and performance a test project was created, implementing a number of image processing tasks using the four GPU programming models. The test project was designed as a library, where the 4 investigated APIs could be replaced at compile-time and new operations could be easily added. The implemented reference algorithms form a pipeline for processing images from polarization cameras. The targeted platforms were mid- to high-end desktop PCs as well as embedded single board platforms ranging from Odroid to Nvidia Jetson. On all devices, either MSVC 19.x or GCC 7+ were used as host compilers. CUDA tests were compiled with NVCC and SYCL was represented by ComputeCpp and hipSYCL depending on the device.The direct comparison of the APIs, done for this work, cumulates into a decision matrix to aid organizations in their process of selecting an offloading API. It shows, for example, that CUDA and SYCL are comparable in terms of development cost, support of modern C++ and ease of integration in existing code bases. When considering modern standard adoption and GPU portability Vulkan has advantages, while OpenCL and SYCL can run on CPUs and FPGAs. In the tooling category, CUDA has the most specialized and effective tools whereas Vulkan has almost no compute specific tools available. CUDA and Vulkan provide the best performance (on the tested devices), while Vulkan was able to outperform CUDA on a Nvidia Jetson.It becomes clear that all four APIs have their advantages and may be suitable for different applications. Vulkan is the API of choice in mobile consumer applications. CUDA is convenient for fast development but only if it is feasible to support Nvidia GPUs only. For AMD GPU support the CUDA-like HIP can be used, although lacking Windows support and the tool quality on the AMD side. OpenCL might be chosen if a considerable number of different desktop GPUs and FPGAs should be supported. Although some metrics still show room for improvement, SYCL seems to grow into a good all-rounder with all the available implementations. It could benefit from weakening its tight integration with OpenCL to improve support on some platforms. A Vulkan implementation, for example, would open opportunities to target mobile and Apple devices, while hipSYCL could gain the status of a standard-conforming implementation.While these results provide a general and first overview of the differences, the pros, and cons of those APIs, it would be interesting to receive feedback from the Khronos developer community on their experiences and build more mature metrics on it.

Community detection is an advanced graph operation that is used to reveal tightly-knit groups of vertices (aka. communities) in real-world networks. Given the intractability of the problem, efficient heuristics are used in practice. Yet, even the best of these state-of-the-art heuristics can become computationally demanding over large inputs and can generate workloads that exhibit inherent irregularity in data movement on manycore platforms. In this paper, we posit that effective acceleration of the graph community detection operation can be achieved by reducing the cost of data movement through a combined innovation at both software and hardware levels. More specifically, we first propose an efficient software-level parallelization of community detection that uses approximate updates to cleverly exploit a diminishing returns property of the algorithm. Secondly, as a way to augment this innovation at the software layer, we design an efficient Wireless Network on Chip (WiNoC) architecture that is suited to handle the irregular on-chip data movements exhibited by the community detection algorithm under both unicast- and broadcast-heavy cache coherence protocols. Experimental results show that our resulting WiNoC-enabled manycore platform achieves on average 52% savings in execution time, without compromising on the quality of the outputs, when compared to a traditional manycore platform designed with a wireline mesh NoC and running community detection without employing approximate updates.

General Purpose Graphic Processing Unit(GPGPU) is used widely for achieving\nhigh performance or high throughput in parallel programming. This capability of\nGPGPUs is very famous in the new era and mostly used for scientific computing\nwhich requires more processing power than normal personal computers. Therefore,\nmost of the programmers, researchers and industry use this new concept for\ntheir work. However, achieving high-performance or high-throughput using GPGPUs\nare not an easy task compared with conventional programming concepts in the CPU\nside. In this research, the CPU's cache memory optimization techniques have\nbeen adopted to the GPGPU's cache memory to identify rare performance\nimprovement techniques compared to GPGPU's best practices. The cache\noptimization techniques of blocking, loop fusion, array merging and array\ntranspose were tested on GPGPUs for finding suitability of these techniques.\nFinally, we identified that some of the CPU cache optimization techniques go\nwell with the cache memory system of the GPGPU and shows performance\nimprovements while some others show the opposite effect on the GPGPUs compared\nwith the CPUs.\n

General Purpose Graphics Processing Units (GPGPU) have become a popular platform to accelerate high performance applications. Although they provide exceptional computing power, GPGPU impose significant pressure on the off-chip memory system. Evaluating, understanding, and improving GPGPU data access delay has become an important research topic in high-performance computing. In this study, we utilize the newly proposed GPGPU/C-AMAT (Concurrent Average Memory Access Time) model to quantitatively evaluate GPGPU memory performance. Specifically, we extend the current C-AMAT model to include a GPGPU-specific modeling component and then provide its evaluation results.

Milk production and reproductive performance are two major determinants of dairy cow profitability. There is much debate among dairy producers and researchers about possible antagonism between high milk production and reproductive performance. There are questions about possible conflicts of genetic selection for production and fertility and whether management can meet the needs of cows for both high production and timely and efficient pregnancy. This paper reviews and critiques data on measuring the association of the level of milk production with pregnancy rate in dairy cows. Many papers refer to a decline in fertility in dairy cattle over the last 20 to 30 years but valid primary data to support this assertion are scarce. While there are reports from 50 to 80 years ago expressing concern about reproductive performance and the effect of increasing production on it, it seems that measures of reproduction in large datasets only began to decline in the mid-1970s to mid-1980s (Nebel and McGillard, 1993; Lucy, 2001; Stevenson, 2001). This coincided with acceleration of trends toward fewer, larger dairy farms with more non-family employees and increasing use of technologies to assist management. Despite the continued march of increasing production per cow per year, recent data suggest that the trend in the US in some of the same measures of reproduction has begun to improve (Norman et al., 2009). There are a few frequently referred-to datasets (e.g., Butler, 1998; Royal et al., 2000; Lucy 2001) that show an apparent decrease in conception risk over the last 50 years, during which time milk production per cow has increased substantially. These data warrant scrutiny. Temporal associations do not imply causation. To the extent that producers abandon breeding on low producing animals but continue to inseminate high producing animals, it is not surprising that there is an apparent association between higher milk yield and a higher number of artifical insemination (AI) per pregnancy. Also, many aspects of dairy production have changed in the last two generations, so caution is needed in inferring a cause-and-effect relationship between high production and decreased reproductive performance when the potential for confounding of the relationship is high. The weaknesses and pitfalls of causal reasoning relative to study design and analysis in the context of the present question have been well discussed by Morton (2006) and Bello et al. (2012). Some key points include: • Failure to account for confounders: many studies ignored other variables that have changed over time along with production and reproduction (e.g., herd size, the skill and experience of farm personnel, increasing confinement on concrete floors which may impair estrus expression), leaving these analyses susceptible to confounding and therefore overestimation of the strength of the effect of production. For example, at the cow level it may be body condition that is a determinant of reproductive function rather than milk yield (Santos et al., 2009), but the former is often not available in large datasets.

Recently, GPGPU (General Purpose computation on Graphics Processing Units) has become popular with great success, especially in scientific fields such as fluid dynamics, image processing, and visualization using particle methods. In this paper, we discuss how the GPGPU is used in implementations of parallel ant colony optimization (ACO) for fast solution of quadratic assignment problems (QAPs). As for the ACO, we use the cunning ant system (cAS) which is one of the most promising ACO algorithms.

Impacted by complex sedimentary and diagenetic characteristics, bioclastic limestone reservoirs develop pore with diverse types, and pore-throat with complex structures, which put difficulty in classification evaluation, and further restrict the efficient development of the reservoirs. Comprehensively utilizing the data of core, well-logging, seismic, cast thin section, high pressure mercury injection and production performance, taking the lower member of Mishrif Formation in the Middle East H oilfield as an example, the differential diagenesis characteristics of bioclastic limestone reservoirs are clarified, and reservoir genetic classification evaluation system with sedimentary diagenesis control and production dynamic is established, the characteristics of reservoir distribution are then revealed based on the associative analysis of well-logging and seismic. The results show that the sedimentary microfacies determine the original fabric structures and bioclastic types of Mishrif Formation, and thus further control the diagenesis sequence and intensity. There are four types of differential diagenesis characteristics: high energy microfacies developed with non-selective dissolution, medium energy microfacies superimposed with selective dissolution, medium-low energy microfacies developed with moderate cementation and moderate -weak dolomitization, low energy microfacies superimposed strong cementation and moderate dolomitization, each type of reservoir develops pore with similar combinations and pore-throat with similar structures. Based on the impact of sedimentary diagenesis, reservoir physical properties and their control on productivity, the bioclastic limestone reservoirs in the studied area are divided into six categories, and the density and deep resistivity identification crossplot is also constructed. Under the constraints of sedimentary microfacies, combined with seismic cloud-transformation physical property inversion method, the distribution characteristics of various types of reservoirs are described. Type I and II reservoirs with medium-high porosity, high permeability and high productivity are mainly developed in the rudist shoal and bioclastic-arene shoal on the platform edge in MB2-1, MB2-2 and MC1-2 layers. The bioclastic limestone of Mishrif Formation is the main production layer in the Middle East, and the research above is of guiding significance for the development of similar reservoirs.KeywordsBioclastic limestoneSedimentary microfaciesDifferential diagenesisGenetic classificationDistribution characteristics

A system architecture with high-density general purpose graphic processing unit (GPGPU) is emerging as a promising solution that can offer high compute performance and performance-per-watt for building cluster supercomputers. The raw compute power of these heterogeneous systems greatly exceeds the current prevailing homogenous systems, motivating their rapid adoption. These heterogeneous systems do however increase the complexity of developing parallel applications and there is a need to investigate the compute performances and associated power consumption of common benchmarks and scientific computing applications. In this paper, we present the performance and power studies through using the Dell C4130 server that integrates up to 4 GPGPU cards and NVIDIA GPGPU K80 is used. The high performance Linpack (HPL) and molecular dynamics (MD) simulators including NAMD, LAMMPS and GROMACS are tested. Through comparing 4-K80 and 2-Xeon E5-2690 v3 systems, we show that: (1) for HPL tests, the 4- GPU server delivers up to 7 TFLOPS that is 9 times faster than the 2-CPU system and its power efficiency is 4 GFLOPS per Watt, (2) for MD tests, NAMD on 4-GPU server achieves 7.8 times speedup and it uses 2.3 times power consumption compared to 2-CPU system, and LAMMPS achieves 16 times speedup and it uses 2.6 times power consumption, and GROMACS achieves 3.3 times speed up and it uses 2.6 times power consumption. These preliminary results demonstrated that the novel high-density multi-GPGPU architecture offers high performances for computing intensive applications and molecular simulators with superior power efficiencies in a space efficient design. In future, such heterogeneous architecture could be a powerful alternative solution for next generation supercomputer systems.

Practical Mechanisms for Reducing Processor–Memory Data Movement in Modern Workloads

Both small satellites (e.g. CubeSats) and sUAS (small Unoccupied Aerial Systems) have a rapidly growing number of potential missions and can serve as platforms for a wide range of uses in science, communications, and remote sensing alone or together. The challenge is integrating these systems quickly and reliably with efficient payload operations. While much work has been completed to define and make flight control and operations available as open systems, fewer options exist for instrumentation. Some options are available for specific domains. For example, ROS (Robot Operating System) is used for many UAV (Unoccupied Aerial Vehicle) projects, but interdisciplinary use cases are non-trivial for projects that migrate payloads between UAVs and CubeSats or coordinate UAV and CubeSat joint missions. Common objectives and careful flight and ground configuration for both UAVs and CubeSats could provide a Common Instrument Stack Architecture (CISA). Many of the basic instrument integration objectives for CubeSats and sUAS share common requirements. The goal for the research architectures we are investigating, is to compare combinations of stack layers including: 1) the use of open source real-time operating systems (RTOS), such as FreeRTOS and Linux with real-time extensions, with 2) open middleware, such as ROS, cFS (core Flight System) or F Prime, and 3) image co-processing firmware. Previously developed and tested FPGA (Field Programmable Gate Array) and GP-GPU (General Purpose Graphics Processing Units) firmware for sUAS sensor networks will be integrated with CISA for performance testing. Ideally, we envision this architecture working for sensor networked flight instruments (sUAS and CubeSat) as well as ground systems (e.g. sUAS traffic management and CubeSat ground operations). To start, we are installing and evaluating the leading open-source middleware options in use for both UAVs and CubeSats integrated with our multi-core, GP-GPU, DPS, and FPGA image processing use cases to assess throughput, memory, I/O, storage, and power consumption. Our intent is to evaluate the relative merits of the underlying hardware architecture by running our prototype CISA (Common Instrument System Architecture) on off-the-shelf multi-core, GP-GPU, and FPGA SoCs (Systems-on-Chip) that have flown or are proposed for space flight, are in use with UAVs and provide best power efficiency and performance. This reference CISA stack composed of an SoC, operating system, co-processing, and middleware is hypothesized to allow future projects to migrate instrumentation and sensor payloads from UAVs to CubeSats easily and efficiently. Migration would provide continuity and scaling for research and science missions as well as joint operations. Along with objective metrics such as power and performance, the project is evaluating subjective metrics such as simplicity of integration, configuration, and interfacing common sensors.

High-level GPU graph processing frameworks are an attractive alternative for achieving both high productivity and high performance. Hence, several high-level frameworks for graph processing on GPUs have been developed. In this paper, we develop an approach to graph processing on GPUs that seeks to overcome some of the performance limitations of existing frameworks. It uses multiple data representation and execution strategies for dense versus sparse vertex frontiers, dependent on the fraction of active graph vertices. A two-phase edge processing approach trades off extra data movement for improved load balancing across GPU threads, by using a 2D blocked representation for edge data. Experimental results demonstrate performance improvement over current state-of-the-art GPU graph processing frameworks for many benchmark programs and data sets.

GPU는 저렴한 비용으로 쉽게 대규모 데이터 병렬성을 활용할 수 있는 장점을 갖고 있어 많은 고성능 컴퓨팅 응용 분야에서 사용되고 있는 추세다. 행렬의 고유벡터를 구하는 power method는 웹 페이지의 중요도를 계산하는 PageRank 알고리즘 등 여러 응용 분야에서 활용되고 있는 방법으로써, 본 연구에서는 power method를 GPU에서 병렬화하여 구현하였으며, 성능을 최적화하기 위한 개선 방법을 제시하였다. Power method는 행렬과 벡터의 곱셈 연산이 반복적으로 수행되며 GPU에서 쉽게 병렬화가 가능하다. 그러나, 고유벡터의 수렴 여부 판단을 위한 연산 등의 작업과 다음 곱셈을 위한 벡터 크기의 조정 등의 작업이 부가적으로 필요하며, 이러한 작업은 GPU 내의 커널 코드를 여러 차례 호출하고 불필요한 데이터 이동을 유발하는 문제점이 있다. 본 연구에서는 커널 호출 회수를 줄이고 스레드 배치를 최적함과 동시에 수렴 여부 판단을 위한 연산을 최적함으로써 power method의 성능을 향상시켰다. GPU computing is emerging in high performance application area since it can easily exploit massive parallelism in a way of cost-effective computing. The power method which finds the eigen vector of a given matrix is widely used in various applications such as PageRank for calculating importance of web pages. In this research we made the power method efficiently parallelized on GPU and also suggested how it can be improved to enhance its performance. The power method mainly consists of matrix-vector product and it can be easily parallelized. However, it should decide the convergence of the eigen vector and need scaling of the vector subsequently. Such operations incur several calls to GPU kernels and data movement between host and GPU memories. We improved the performance of the power method by means of reduced calls to GPU kernels, optimized thread allocation and enhanced decision operation for the convergence.

Nowadays graphics processing units (GPUs) have become popular parallel computing platforms known as General-Purpose GPU (GPGPU) computing. GPUs thereby are chosen by some security researchers as cryptographic accelerators to secure massive volumes of transactions. However, their security issues are ignored in spite of their popularity and performance. There are some possible information leakages faced with malicious attacks or even in the normal GPU computing. Our objective is to secure the confidentiality of cryptographic keys in GPU computing environments and provide easy-to-use programming with few constraints. In this paper, we propose a prototype in Linux, a system of GPGPU computing solution empowered by GPU virtualization technology, which keeps encrypted keys in guest machine to protect secret keys from leakage even in the event of full system compromise. With the API interception and redirection of CUDA, applications in Virtual Machines (VMs) can access the GPU device in a transparent way. Besides, we use virtio, a dedicated virtual I/O device, to transfer data between virtual and host machines in high performance. In our current study, we evaluate our prototype with the GPU implementation of ECC. We show that it can protect private keys of GPU cryptographic computation and it also incurs low performance penalty compared with the native environment, therefore demonstrating the prototype is secure and requires reasonable overhead.

Modern computer systems feature multiple homogeneous or heterogeneous computing units with deep memory hierarchies, and expect a high degree of thread-level parallelism from the software. Exploitation of data locality is critical to achieving scalable parallelism, but adds a significant dimension of complexity to performance optimization of parallel programs. This is especially true for programming models where locality is implicit and opaque to programmers. In this paper, we introduce the hierarchical place tree (HPT) model as a portable abstraction for task parallelism and data movement. The HPT model supports co-allocation of data and computation at multiple levels of a memory hierarchy. It can be viewed as a generalization of concepts from the Sequoia and X10 programming models, resulting in capabilities that are not supported by either. Compared to Sequoia, HPT supports three kinds of data movement in a memory hierarchy rather than just explicit data transfer between adjacent levels, as well as dynamic task scheduling rather than static task assignment. Compared to X10, HPT provides a hierarchical notion of places for both computation and data mapping. We describe our work-in-progress on implementing the HPT model in the Habanero-Java (HJ) compiler and runtime system. Preliminary results on general-purpose multicore processors and GPU accelerators indicate that the HPT model can be a promising portable abstraction for future multicore processors.

High-performance applications running on current and future architectures are mostly performance-limited by the cost of data movement, vertically through the memory hierarchy of a node or between CPU host and accelerator, and horizontally across nodes. In this talk, we discuss the role of packed data layout in optimizing data movement across a variety of different architectures (CPU and GPU) and memory systems. Conceptually, a high performance application is defined as operations on a unit of data and parallelism that is designed for efficient vertical and horizontal data movement, and can be tailored to match the requirements of an application and target architecture. Integrating data layout abstractions and optimizations into programming systems provides critical technology for achieving performance portability across the diversity of high-performance architectures arising in the exascale era.