A Novel Quaternary Half Subtractor Using 2:1 Multiplexer

Multi-valued logic (MVL) is that logic which has two or more logic values. In complex digital circuits, MVL (mainly Ternary logic) offers several advantages over binary logic. Carbon Nanotube Field Effect Transistor (CNTFET) technology is ideal to implement ternary logic circuits because of the threshold voltage of CNTFETs depends on the physical dimensions (chirality) of their channel. This work presents the implementation of a three-bit Ternary Prefix Adder using CNTFET technology. In this paper, a carry propagate-generate concept is used in order to implement the ternary prefix adder. A Kogge-Stone based prefix network is preferred for carry computation due to its high performance. A low power enoder is used for reducing the overall power of the adder. HSpice tool is chosen for designing this system. Simulation results show that there is a significant reduction in Power Delay Product (PDP) by 28 % compared to all other previous works.

This paper investigates the performance of Single Edge Triggered D-Flip flop (SET D-FF) using Carbon Nanotube Field Effect Transistors (CNFETs). The circuit performance of CNFET model has been compared with that of silicon based MOSFET model. CNFET circuit models are tested for various substrate bias voltages in sub threshold region. A 10 Transistor version of SET D-FF is implemented using PTM 32nm CMOS model and Stanford single-walled CNFET model and simulated using HSPICE. The performance parameter under investigation is Power Delay Product (PDP). The comparative simulation result at various frequencies show that CNFET SET DFFs have superior Power Delay Product over MOSFET SET DFFs.

Carbon nanotubes (CNT) field-effect transistor (CNTFET) could be a possible alternative to CMOS technology for future VLSI applications. In this work, a comparative study has been carried out on the effects of technology nodes and logic styles on power dissipation, delay, leakages, etc. The technology nodes that are considered here are 90 nm and 32 nm MOSFET technology, and 32 nm CNTFET technology. The logic families considered here are the conventional complementary metal-oxide-semiconductor (CMOS), complementary pass transistor logic (CPL) and transmission gate (TG). The digital circuits considered are NAND, NOR, XOR and MUX gates. HSPICE simulations have been carried out and observed that at 32 nm CNTFET technology, the least power, worst-case delay and least PDP are found as 15.5 nW, 3.11 ps and 0.048 aJ, respectively. It is witnessed that CNTFET-based logics are superior compared to other logic families at different technology nodes.

Enhancing high-speed digital systems: MVL circuit design with CNTFET and RRAM

Software-Defined Networking (SDN) revolutionizes network management by decoupling control plane functionality from data plane devices, enabling the centralized control and programmability of network behavior. This paper uses the ternary system to improve the Central Processing Unit (CPU) inside the SDN controller to enhance network management. The Multiple-Valued Logic (MVL) circuit shows remarkable improvement compared to the binary circuit regarding the chip area, propagation delay, and energy consumption. Moreover, the Carbon Nanotube Field-Effect Transistor (CNTFET) shows improvement compared to other transistor technologies regarding energy efficiency and circuit speed. To the best of our knowledge, this is the first time that a ternary design has been applied inside the CPU of an SDN controller. Earlier studies focused on Ternary Content-Addressable Memory (TCAM) in SDN. This paper proposes a new 1-trit Ternary Full Adder (TFA) to decrease the propagation delay and the Power-Delay Product (PDP). The proposed design is compared to the latest 17 designs, including 15 designs that are 1-trit TFA CNTFET-based, 2-bit binary FA FinFET-based, and 2-bit binary FA CMOS-based, using the HSPICE simulator, to optimize the CPU utilization in SDN environments, thereby enhancing programmability. The results show the success of the proposed design in reducing the propagation delays by over 99% compared to the 2-bit binary FA CMOS-based design, over 78% compared to the 2-bit binary FA FinFET-based design, over 91% compared to the worst-case TFA, and over 49% compared to the best-case TFAs.

A lot of research has been done on multiple-valued logic (MVL) such as ternary logic in these years. MVL reduces the number of necessary operations and also decreases the chip area that would be used. Carbon nanotube field effect transistors (CNTFETs) are considered a viable alternative for silicon transistors (MOSFETs). Combining carbon nanotube transistors and MVL can produce a unique design that is faster and more flexible. In this paper, we design a new half adder and a new multiplier by nanotechnology using a ternary logic, which decreases the power consumption and chip surface and raises the speed. The presented design is simulated using CNTFET of Stanford University and HSPICE software, and the results are compared with those of other studies.

Carbon Nanotube Field Effect Transistors (CNFETs) are considered to be an ideal choice for implementation of Multi-valued logic circuits, as by using CNFETs multiple thresholds can be obtained by altering the dimensions of the carbon nanotube. Implementation of various CNFET based Ternary Arithmetic circuits like Adders and Multipliers is extensively researched upon. The existing design for a CNFET based Multiplier is based on the classical Wallace approach which uses 3:1 Multiplexers along with Unary operators of Ternary logic. In this paper, design of a novel low power Single-Trit Multiplier and a Three-Trit Multiplier is proposed which uses a 2:1 Multiplexer based design approach. This design shows considerable improvement in terms of power consumption. From the Hspice simulation results, it is noted that the proposed Single-Trit Multiplier design results in up to 99% reduction in Power consumption, 56% reduction in Delay and 99.8% reduction in Power-Delay Product (PDP) when compared to an existing Single-Trit Multiplier. Proposed Three-Trit Multiplier results in savings in power consumption up to 98.2% and 98. 5% reduction in PDP when compared to Three-Trit Multiplier design in the existing literature.

Multi-valued logic arbiter PUF designs based on CNTFETs

This paper proposes an energy efficient Carbon Nanotube Field Effect Transistor (CNFET) based architecture of 4-input Look-up Table (LUT), a building block of Field programmable gate arrays. HSPICE simulation based on Berkeley Predictive Technology Model (BPTM) for 32 nm channel length device shows that for Iso-area, the CNFET based LUT is 98% more leakage power efficient than the LUT implemented in the bulk CMOS. Similarly, at operating frequency of 250 MHz and at supply voltage of 0.9 V compared to bulk CMOS LUT, the proposed Hybrid LUT and CNFET LUT provides 36% and 53% improvement in power delay product respectively.

In this work, we have presented the design of voltage level shifter using carbon nanotube field effect transistors (CNTFETs). The proposed design is capable of converting two input voltage levels to two output voltage levels. The threshold voltage of CNTFETs is suitably chosen to achieve the desired output. The proposed design can perform both up and down shifting which is very useful in the system-on-a-chip design to interface with other peripherals. It exhibits lower delay and power delay product in comparison with the existing complementary metal–oxide–semiconductor-based voltage level shifters. The proposed circuit is very effective as it eliminates the requirement of additional voltage level shifter for designing systems with multi-power supply voltage domain in the nanoscale regime. The design has been analyzed for different process, voltage and temperature corners. It has been shown that the design works perfectly with [Formula: see text] variation in the diameter of the carbon nanotubes used in the CNTFET. The performance varies slightly with [Formula: see text] variation in operating voltage. Our analysis shows that the design is thermally stable for a wide variation in operating temperature.

The VLSI based circuits often pose challenges in the form of various faults (such as transient faults, permanent faults, stuck-at-faults). These faults appear even after testing also. They occur because of reduction in the size of the circuit or during realtime implementation, as these faults are difficult to detect. It is very important to detect and rectify all such faults to make the system foolproof and achieve expected functionality. In this paper, 12 transistors based, full adder circuit (12T-FAC) using Carbon Nanotube Field Effect Transistor (CNFET) technology is proposed. The proposed design based on CNFET provides high fault resistance towards transient, permanent faults and works with least power, delay and power-delay product (PDP). Later, features like fault detection and correction circuit have been added in 12T-FAC. The final version of full adder circuit capable of correcting errors has been used in designing applications like multipliers. The proposed full adder circuit was designed with CNFET technology, simulated at 32 nm with supply voltage +0.9 V using the Cadence Virtuoso CAD tool. The model used is Stanford PTM.

An ultra-low power 8-Transistor Modified Gate Diffusion Input (MGDI) Carbon Nano Tube Field Effect Transistor (CNTFET) Full Adder (FA) has been presented in this paper. The proposed 8-T MGDI CNTFET Full Adder outperforms other adders in terms of Power Consumption, Propagation Delay and the PDP at different levels of Power Supply and Temperatures. The power consumption of the proposed 10 nm CNTFET 8-T MGDI Full Adder at 27°C is 1.96 nW. The proposed CNTFET FA exhibits 60.32% improvement in Power Consumption when compared to the existing 10 nm FINFET 8-T MGDI Full Adder. The propagation Delay of the proposed FA is 42.16 ps and an improvement of 57.68% is noticed over the existing FA. The Power Delay Product of the proposed 10 nm CNTFET 8-T MGDI FA is 82.63 × 10−21 Jules, whereas the PDP of the 10 nm FINFET 8-T MGDI FA is 492.07 × 10−21 Jules. The PDP of the proposed 10 nm CNTFET 8-T MGDI Full Adder exhibits 83.21% improvement when compared to the 10 nm FINFET 8-T MGDI FA.

Novel carbon nanotube field effect transistor with graded double halo channel

Due to extraordinary physical and electrical properties, carbon nanotubes have become one of the most promising technologies that might someday pick up where conventional CMOS devices leave off. This paper details analysis of power and delay performance of carbon nanotube field effect transistor- based universal logic gates (NAND and NOR gates). Though electrolyte-gated carbon nanotube field effect transistor have exhibited the highest performance than top-gated and back-gated carbon nanotube field effect transistor, the work demonstrates that energy delay product and switching time performance of 30nm channel length top-gated carbon nanotube field effect transistor - based NAND gate is much better than 20nm channel length electrolyte-gated carbon nanotube field effect transistor technology. As the performance of p type carbon nanotube field effect transistor is better than n type carbon nanotube field effect transistor, 30nm channel length top-gated carbon nanotube field effect transistor-based NOR gate is 4% faster than corresponding NAND gate and its energy delay product is 46% lesser than that of NAND gate.

Nowadays, portable multimedia devices have been widely used in low-power structures. Additionally, using approximate computing and multiple-valued logic (MVL) can lead to lower power consumption. Carbon nanotube field effect transistor (CNTFET), with a determinable threshold voltage, is an appropriate choice for designing MVL circuits. In this study, a new approximate ternary full adder is presented based on CNTFET switching logic with the aim of reducing area and energy consumption. The results obtained by the Synopsys HSPICE simulator with the Stanford 32 nm CNTFET technology show that the average power consumption, delay, and energy consumption of the proposed designs are significantly lower than the other conventional and state-of-the-art CNTFET-based ternary circuits. In addition, the proposed ternary full adder is applied to reduce the steps of a ternary multiplier structure and some important metrics such as normalized error distance and energy-error trade-off are calculated to evaluate the efficiency of the proposed circuits. The layout of the proposed design is also plotted to estimate area consumption. Moreover, the approximate design is used for image processing applications such as image multiplying and image blending and the results are accordingly compared with the exact outputs. Similarly, the evaluated peak signal-to-noise ratio and mean structural similarity index metric indicate that the proposed approximate full adder has a proper accuracy for image processing applications.