A Novel ReRAM-Based Processing-in-Memory Architecture for Graph Traversal

Processing-in-memory (PIM) exploits massive parallelism with high energy efficiency and becomes a promising solution to the von Neumann bottleneck. Recently, the emerging metal-oxide resistive random access memory (RRAM) shows its potential to construct a PIM architecture, because several stateful logic operations, e.g., IMP and NOR, can be executed in an RRAM crossbar in parallel. Previous synthesis flows focus on improving latency with stateful logic operations, but they ignore that the memory should be used primarily for storage. i.e., most of the area in the crossbar is used for computation but not storage. In this situation, storage and computation still have to be separated into different crossbars, which leads to considerable data transfer overhead and limited parallelism. In this work, we define the ratio of storage in a crossbar as area utilization. We aim to improve the area utilization without throughput loss by proposing STAR, a novel synthesis flow for the stateful logic. We present two optimization strategies to reduce the computation area in STAR. First, we reduce the area for redundant inputs. For the shared constants among different rows (or columns), we encode them as immediate values into the control signals without writing them into the crossbar at runtime. For the other inputs, we only store one copy of them in the crossbar. Second, we reduce the area for intermediate variables by reusing invalid cells. And we design a scheduling algorithm to find a computation sequence with the minimal variable erasing cycles. Invalid primary inputs can also be erased in this algorithm. Furthermore, we present a case study of the image convolution to demonstrate the effectiveness of STAR. Experimental evaluation shows that STAR achieves 33.03% more area utilization and a 1.43x throughput compared to SIMPLER, the state-of-the-art stateful logic synthesis flow. Our image convolution implementation also provides 78.36% more area utilization and a 1.48x throughput compared with IMAGING, the state-of-the-art stateful logic-based image processing accelerator.

Processing-in-memory (PIM) is a promising solution to address the "memory wall" challenges for future computer systems. Prior proposed PIM architectures put additional computation logic in or near memory. The emerging metal-oxide resistive random access memory (ReRAM) has showed its potential to be used for main memory. Moreover, with its crossbar array structure, ReRAM can perform matrix-vector multiplication efficiently, and has been widely studied to accelerate neural network (NN) applications. In this work, we propose a novel PIM architecture, called PRIME, to accelerate NN applications in ReRAM based main memory. In PRIME, a portion of ReRAM crossbar arrays can be configured as accelerators for NN applications or as normal memory for a larger memory space. We provide microarchitecture and circuit designs to enable the morphable functions with an insignificant area overhead. We also design a software/hardware interface for software developers to implement various NNs on PRIME. Benefiting from both the PIM architecture and the efficiency of using ReRAM for NN computation, PRIME distinguishes itself from prior work on NN acceleration, with significant performance improvement and energy saving. Our experimental results show that, compared with a state-of-the-art neural processing unit design, PRIME improves the performance by ~2360× and the energy consumption by ~895×, across the evaluated machine learning benchmarks.

Processing-in-memory (PIM) is a promising solution to address the "memory wall" challenges for future computer systems. Prior proposed PIM architectures put additional computation logic in or near memory. The emerging metal-oxide resistive random access memory (ReRAM) has showed its potential to be used for main memory. Moreover, with its crossbar array structure, ReRAM can perform matrix-vector multiplication efficiently, and has been widely studied to accelerate neural network (NN) applications. In this work, we propose a novel PIM architecture, called PRIME, to accelerate NN applications in ReRAM based main memory. In PRIME, a portion of ReRAM crossbar arrays can be configured as accelerators for NN applications or as normal memory for a larger memory space. We provide microarchitecture and circuit designs to enable the morphable functions with an insignificant area overhead. We also design a software/hardware interface for software developers to implement various NNs on PRIME. Benefiting from both the PIM architecture and the efficiency of using ReRAM for NN computation, PRIME distinguishes itself from prior work on NN acceleration, with significant performance improvement and energy saving. Our experimental results show that, compared with a state-of-the-art neural processing unit design, PRIME improves the performance by ~2360x and the energy consumption by ~895x, across the evaluated machine learning benchmarks.

Resistance switching characteristics, observed in metal oxide thin films, has recently attracted a great deal of attention to develop next generation low power, low cost, high speed, rugged and nonvolatile resistive random access memory (RRAM) devices. The memory effect in these materials is realized through the switching of the resistance of their thin films between two states of high and low resistances. Amongst the known metal oxides currently being explored for the development of RRAM, ZnO has been demonstrated to be a potential candidate. ZnO is an n‐type wide bandgap semiconductor and is highly transparent in the visible spectral region. Moreover its conductivity can be tailored in a broad range from metal like to insulator like by suitable impurity doping. Therefore it is possible to develop a fully transparent RRAM entirely based on ZnO. In this paper we report growth of a novel transparent RRAM devices based on ZnO and its variants. We studied the resistive switching characteristics of these devices and associated conduction mechanisms responsible for the switching. The details of this study will be presented in the paper (© 2010 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

In this study, we demonstrated the integration of black phosphorus (BP) nanoflakes in a resistive random access memory (RRAM) with a facile and complementary metal-oxide-semiconductor-compatible process. The solution-processed BP nanoflakes embedded in polystyrene (PS) as an active layer were sandwiched between aluminum electrodes (Al/BP:PS/Al). The device shows a figure of merit with typical bipolar behavior and forming-free characteristics as well as excellent memory performances such as nonvolatile, low operation voltage (1.75 V) and high ON/OFF ratio (>102) as well as the long retention time (>1500 s). The improved device performances were attributed to the formation of effective trap sites from the hybrid structure of the active layer (BP:PS), especially the BP nanoflakes and the partly oxidized species (PxOy). Moreover, the extrinsic aluminum oxide layer was observed after the device operation. The mechanism of switching behavior was further unveiled through the carrier transport models, which confirms the conductive mechanisms of space-charge-limited current and Ohmic conductance at high resistance state (HRS) and low resistance state, respectively. Additionally, in the high electric field at HRS, the transfer curve was well fitted with the Poole–Frenkel emission model, which could be attributed to the formation of the aluminum oxide layer. Accordingly, both the trapping/de-trapping of carriers and the formation/rupture of conductive filaments were introduced as transport mechanisms in our devices. Although the partial PxOy species on BP were inevitable during the liquid phase exfoliation process, which was regarded as the disadvantages for various applications, it turns to a key point for improving performances in memory devices. The proposed approach to integrating BP nanoflakes in the active layer of the RRAM device could pave the way for next-generation memory devices.

We have carried out microscopic resistance profile measurements by scanning probe microscopy (SPM) and model analyses on a symmetric thin-film electrical pulse induced resistance change (EPIR) device having a Pr0.7Ca0.3MnO3(PCMO) active layer. The film morphology and surface potential distribution has been examined by atomic force microscopy (AFM) and surface scanning Kelvin probe microscopy (SKPM). Resistance distribution profiles across the device indicate contribution to the resistance switching from three parts of the device: the two PCMO interface regions within ∼1–3 μ m around the metal electrode/PCMO contacts, and the bulk PCMO material. Such an EPIR device showed a symmetric resistance switching behavior under electric pulsing at room temperature. This research indicates that the EPIR device may be used as a nonvolatile resistive random access memory (RRAM) device with different operation modes by controlling electric pulse voltage. The result is also important for understanding the resistance switching behavior in the EPIR device.

To enhance the system integrity of FPGA-based embedded systems on hardware design, we propose a hardware security scheme for nonvolatile resistive random access memory (RRAM) based FPGA, in which internal block RAM (BRAMs) are used for configuration and temporary data storage. The proposed scheme loads obfuscated configurations into nonvolatile BRAMs to protect design data from physical attacks and utilizes Chip DNA to enable logic function.

The resistive switching characteristics of Pt/CeOx/TiN memory devices are investigated for potential applications in nonvolatile resistive random access memory (RRAM). The X-ray diffraction characteristics of the sputtered CeOx layer indicate the formation of nanocrystalline single-phase CeO2 with a cubic fluorite structure. The existence of oxygen vacancies in the Pt/CeOx/TiN memory device was determined by X-ray photoelectron spectroscopic studies, while the presence of an interfacial layer between CeOx and the TiN bottom electrode was investigated by X-ray diffraction and high resolution transmission electron microscopy. The TiON layer formed at the TiN/CeOx interface seems to play a key role in the resistive switching mechanism of the device. The present CeOx-based device shows excellent bipolar resistive switching characteristics, including a low operation current (100 µA), high ON/OFF resistance ratio (∼105), and good retention/stress characteristics at both room temperature and 85 °C.

Application of ion-implantation for improved non-volatile resistive random access memory (ReRAM)

Recently, NiO film of metal-oxide-metal (MOM) structure 1a has drawn much attention because it shows reproducible resistance switching phenomena applicable to next generation nonvolatile resistive random access memory (ReRAM) device. The resistance switching phenomenon, that is, a drastic change in resistance between a high-resistance state (OFFstate) and low resistance state (ON-state) in current-voltage (I-V) characteristic of MOM structure, has been observed in binary oxides such as NiO, 1 TiO2, 2 Nb2O5, 3 Cr-doped SrZrO3, 4 Pr1-xCaMnO3, 5 and chalcogenide semiconductors although exact origin was unsolved. Among these materials, the binary oxide is the first consideration for the application due to the relatively simple fabrication process. In the case of a device fabrication, the self-limiting process of atomic layer deposition (ALD) may be very important for the growth of NiO films because the expected structure of ReRAM device requires the filling process of NiO on the hole or trench-patterned 3-dimensional substrates. Therefore, it is worthwhile to find the optimal ALD process for NiO film growth by using suitable Ni precursors. In general, most of Ni compounds are in solid state at room temperature although highly volatile liquid precursor is highly desirable to obtain conformal film qualities in ALD processes. A number of nickel precursors have been synthesized and examined for preparing Ni and NiO films using metal organic chemical vapor deposition (MOCVD) and ALD during the past years. The ligands for the nickel precursors are carbonyl, 6 β-diketonates, 7 cycolpentadienyl, 8 and alkoxides, 9 N,N'-dialkyl

The mechanism of forming-free bipolar resistive switching in a Zr/CeOx/Pt device was investigated. High-resolution transmission electron microscopy and energy-dispersive spectroscopy analysis indicated the formation of a ZrOy layer at the Zr/CeOx interface. X-ray diffraction studies of CeOx films revealed that they consist of nano-polycrystals embedded in a disordered lattice. The observed resistive switching was suggested to be linked with the formation and rupture of conductive filaments constituted by oxygen vacancies in the CeOx film and in the nonstoichiometric ZrOy interfacial layer. X-ray photoelectron spectroscopy study confirmed the presence of oxygen vacancies in both of the said regions. In the low-resistance ON state, the electrical conduction was found to be of ohmic nature, while the high-resistance OFF state was governed by trap-controlled space charge-limited mechanism. The stable resistive switching behavior and long retention times with an acceptable resistance ratio enable the device for its application in future nonvolatile resistive random access memory (RRAM).

The training of neural network (NN) is usually time-consuming and resource intensive. Memristor has shown its potential in computation of NN. Especially for the metal-oxide resistive random access memory (RRAM), its crossbar structure and multi-bit characteristic can perform the matrix-vector product in high precision, which is the most common operation of NN. However, there exist two challenges on realizing the training of NN. Firstly, the current architecture can only support the inference phase of training and cannot perform the backpropagation (BP), the weights update of NN. Secondly, the training of NN requires enormous iterations and constantly updates the weights to reach the convergence, which leads to large energy consumption because of lots of write and read operations. In this work, we propose a novel architecture, TIME, and peripheral circuit designs to enable the training of NN in RRAM. TIME supports the BP and the weights update while maximizing the reuse of peripheral circuits for the inference operation on RRAM. Meanwhile, a variability-free tuning scheme and gradually-write circuits are designed to reduce the cost of tuning RRAM. We explore the performance of both SL (supervised learning) and DRL (deep reinforcement learning) in TIME, and a specific mapping method of DRL is also introduced to further improve the energy efficiency. Experimental results show that, in SL, TIME can achieve 5.3× higher energy efficiency on average compared with the most powerful application-specific integrated circuits (ASIC) in the literature. In DRL, TIME can perform averagely 126× higher than GPU in energy efficiency. If the cost of tuning RRAM can be further reduced, TIME have the potential of boosting the energy efficiency by 2 orders of magnitude compared with ASIC.

The first electrically driven random laser diode with nonvolatile resistive random access memory functionality is designed and demonstrated. To illustrate the working principle, a metal–insulator–semiconductor structure based on Pt/MgO/ZnO thin‐film layers is fabricated on indium tin oxide glass. The current–voltage curve of the dual‐function random laser memory (RLM) device exhibits an excellent electrical bistability with a high ON/OFF current ratio (≈107). The random lasing behavior is simultaneously demonstrated by using electrical pumping with the appearance of sharp‐peak emissions and a drastic enhancement of peak intensity. A wide angle‐dependent electroluminescence not only reveals its emitting advantage but also further supports the origin of random lasers. The first proof‐of‐concept presentation of RLM possesses several advantages of dual memory and lasing functions, which enables to open up new avenues to practical applications, such as light emitting memories for electrical and optical communication. This new horizon for the realization of all optical memories should therefore be able to attract academic as well as industrial interests. It is stressed here that the electrical reading of conventional memory array is usually in serial sequence, which limits the maximum data throughput. This hurdle can be overcome by optically readable memory devices.

2 - Metal-oxide resistive random access memory (RRAM) technology: Material and operation details and ramifications

Stochastic neuron is the key for event-based probabilistic neural networks. Here, for the first time, we propose a stochastic neuron based on Metal-Oxide Resistive Random-Access Memory (RRAM). The RRAM's conducting filament with built-in stochasticity is used to mimic the neuron's membrane capacitor that temporally integrates input spikes. A fully asynchronous and capacitor-less neuron circuit is designed, laid out, and simulated. The output spike train of the neuron is shown to obey the Poisson distribution. Using the 65nm CMOS technology node, the area of the neuron is 14 × 5 μm2, which is one ninth size of an 1pF capacitor. The average power consumption of the neuron is 1.289 μW. Finally, an event-based spiking deep belief network (DBN) is evaluated using our neuron design. The DBN is trained using MNIST database. Simulation results show that the DBN is able to recognize the handwritten digits with 90% accuracy.