A packet scheduling algorithm in high performance routers

Packet fair queueing (PFQ) algorithms are packetised versions of generalised processor sharing (GPS), which is an idealised fluid scheduling model with desirable properties in terms of delay bound and fairness. To support a large number of sessions with diverse bandwidth requirements, the grouping architecture, which is scalable, has been proposed to approximate PFQ algorithms. The authors analyse the relationship between the guaranteed service rates and utilisation for cell-based schedulers with the grouping architecture. Based on this analysis, call admission control (CAC) schemes are proposed to provide the guaranteed service rate for each session, and their performance is evaluated and compared in terms of computational complexity.

In order to address the challenge of providing quality of service guarantees in today's network processing systems, the use of efficient scheduling algorithms is required. The efficiency of a scheduler is determined by several factors including its fairness, capability to operate at high speeds, as well as the resources required for its implementation. We present an architecture to support fair scheduling (gigabit FS) considering variable length packets (i. e. for packet forwarding/switching networks) over gigabit links. This high speed scheduler is designed to manage 32 K flows based on an algorithm that yields efficient implementation in hardware by avoiding the complexity of computing the system virtual time function that many packet fair queueing (PFQ) algorithms have proposed. Further, we demonstrate the critical factors in designing an effective scheduling engine at gigabit rates and we present several enhancements together with their associated cost.

Packet scheduling constitutes the core problem in efficient fair allocation of bandwidth to competing flows. To date, numerous algorithms for packet scheduling have been suggested and tested. However, only a few of them are currently deployed. One of the key reasons for rarity of applied packet scheduling methods lies in the complexity of their implementation. This paper describes a family of randomized algorithms for packet scheduling. These algorithms are simple to implement and require small amounts of computation time. Specifically we present an O(1) probabilistic weighted fair queuing algorithm that emits packets from flows with an improved delay jitter. Experimental results of the proposed randomized algorithms suggest that the randomized approach is a viable alternative to the currently deployed deterministic fair queuing algorithms.

Self-Clocked Fair Queueing (SCFQ) algorithm has been considered as an attractive packet scheduling algorithm because of its implementation simplicity, but it has unbounded delay property in some input traffic conditions. In this paper, we propose a Rate Proportional SCFQ (RP-SCFQ) algorithm which is a rate proportional version of SCFQ. If any fair queueing algorithm can be categorized into the rate proportional class and input is constrained by a leaky bucket, its delay is bounded and the same as that of Weighted Fair Queueing (WFQ) which is known as an optimal fair queueing algorithm. RP-SCFQ calculates the timestamps of packets arriving during the transmission of a packet using the current value of system potential updated at every packet departing instant and uses a starting potential when it updates the system potential. By doing so, RP-SCFQ can have the rate proportional property. RP-SCFQ is appropriate for high-speed packet-switched networks since its implementation complexity is low while it guarantees the bounded delay even in the worst-case input traffic conditions.

Only best-effort traffic was supported by traditional packet switching networks, but newer applications need network services that allow an end-client to transport data with performance guarantees. The choice of packet-scheduling algorithm used at switching nodes is crucial in providing Quality of Service (QoS). This paper proposes a downlink packet scheduling algorithm for QoS provisioning in High Speed Downlink Packet Access (HSDPA) based UMTS networks. In HSDPA, a single logical channel is shared amongst multiple contending users. Besides better link utilization, scheduling disciplines seek to achieve fair allocation of this shared resource. However, these two criteria can potentially be in conflict. The scheduling algorithm proposed in this paper, Wireless Fair High Speed Scheduling, addresses this conflict. The basic idea is to allocate the wireless channel fairly amongst users, even during short time scales, according to their data rate requirements. Simulation results show that the proposed scheduling algorithm provides better link utilization, as well as long-term and short-term fairness amongst users, even under heavy load conditions.

Fair scheduling or Fair Queueing (FQ) algorithms have received much attention in recent years because of their ability to provide a wide range of Quality-ofService (QoS) guarantees to end users. In this paper, we present a new analysis method that can statistically model such fair scheduling algorithms under Poisson arrivals and a general packet length distribution. We coin the new term M/G/FQ to describe this analysis method, which fits a broad range of scheduling policies including WFQ, SCFQ, SFQ and SPFQ.

The development of 3G (the 3rd generation telecommunication) value-added services brings higher requirements of Quality of Service (QoS). Wideband Code Division Multiple Access (WCDMA) is one of three 3G standards, and enhancement of QoS for WCDMA Core Network (CN) becomes more and more important for users and carriers. The dissertation focuses on enhancement of QoS for WCDMA CN. The purpose is to realize the DiffServ (Differentiated Services) model of QoS for WCDMA CN. Based on the parallelism characteristic of Network Processors (NPs), the NP programming model is classified as Pool of Threads (POTs) and Hyper Task Chaining (HTC). In this study, an integrated programming model that combines both of the two models was designed. This model has highly efficient and flexible features, and also solves the problems of sharing conflicts and packet ordering. We used this model as the programming model to realize DiffServ QoS for WCDMA CN. The realization mechanism of the DiffServ model mainly consists of buffer management, packet scheduling and packet classification algorithms based on NPs. First, we proposed an adaptive buffer management algorithm called Packet Adaptive Fair Dropping (PAFD), which takes into consideration of both fairness and throughput, and has smooth service curves. Then, an improved packet scheduling algorithm called Priority-based Weighted Fair Queuing (PWFQ) was introduced to ensure the fairness of packet scheduling and reduce queue time of data packets. At the same time, the delay and jitter are also maintained in a small range. Thirdly, a multi-dimensional packet classification algorithm called Classification Based on Network Processors (CBNPs) was designed. It effectively reduces the memory access and storage space, and provides less time and space complexity. Lastly, an integrated hardware and software system of the DiffServ model of QoS for WCDMA CN was proposed. It was implemented on the NP IXP2400. According to the corresponding experiment results, the proposed system significantly enhanced QoS for WCDMA CN. It extensively improves consistent response time, display distortion and sound image synchronization, and thus increases network efficiency and saves network resource.

Low cost broadband services used widely in the recent years increased the demand for multimedia applications. Many of these applications require different quality of service (QoS) in terms of throughput and delay. In the current resource constrained wireless networks, resource management plays a vital role. In order to handle the resources effectively and to increase the QoS, proper packet scheduling algorithms need to be developed. Low latency queuing (LLQ) is a packet scheduling algorithm which combines strict priority queuing (SPQ) to class-based weighted fair queuing (CBWFQ). In this paper, an enhanced low latency queuing (ELLQ) algorithm is proposed in which an additional SPQ is introduced along with the existing SPQ. Further, the QoS is improved by integrating congestion avoidance algorithm with ELLQ. Simulation results using the OPNET modeller show that the proposed algorithm outperforms the existing algorithm in terms of throughput and delay for the multimedia applications.

There is a widespread interest in switching architectures that can scale in capacity with increasing interface transmission rates and higher port counts. Furthermore, packet switches that provide Quality of Service (QoS), such as bandwidth and delay guarantees, to the served user traffic are also highly desired. This report addresses the issue of constructing a high-capacity QoS-capable, multi-module switching node. Output queued switches provide the best performance in terms of throughput as well as QoS but do not scale. Input queued switches, on the other hand, require complex arbitration procedures to achieve the same level of performance. We enumerate the design constraints in the construction of a packet switch and present several approaches to build a system composed of lower-capacity memory and space elements, and analyze their performance. Towards this goal, we establish a new taxonomy for a class of switches, which we call Buffered Clos switches, and present a formal framework for optimal packet switching performance, in terms of both throughput and QoS. Within the taxonomy, we augment the existing combined input-output queueing (CIOQ) systems with Aggregation and Pipelining techniques. Furthermore, we present the design and analysis of a novel parallel packet switch architecture. For the items in the taxonomy, we present algorithms that provide optimal throughput and QoS, in accordance with the above performance framework. While some of the presented ideas are still in the investigative stage, we believe that the current state of the work, especially the formal treatment of switching, will be beneficial to the ongoing research in the field.

Low latency and efficient packet scheduling for streaming applications

Admission control in Flow-Aware Networking (FAN) architectures under GridFTP traffic

Recently, a number of fair queueing algorithms for wireless networks have been proposed. They, however, need perfect channel prediction before transmission and rarely consider a medium access control (MAC) algorithm. In the wireless world, the link level retransmission scheme is popularly used in the MAC layer for recovering channel errors. Therefore, we propose a new wireless fair queueing algorithm that works well with link level retransmission and does not require channel prediction. Through simulation, we showed that our algorithm guarantees throughput and fairness. Also, we found that our algorithm achieves flow separation and compensation.

Analysis of temporal and throughput fair scheduling in multirate WLANs

For pt.I see ibid., p.509-18 (1997). The total implementation complexity of cell schedulers which aim at approximating the generalized processor sharing (GPS) policy is the combination of the complexity of their system-potential function and the complexity involved in sorting the timestamps in order to select the cell with minimum timestamp for transmission. Given that several scheduling algorithms which use a system-potential function of O(1) complexity have been introduced (among them, the minimum-delay self-clocked fair queueing (MD-SCFQ) algorithm achieves optimal delay and excellent fairness properties), the major contribution to the total complexity comes from the task of sorting the timestamps every time a cell is transmitted or received, which is common to all GPS-related schedulers. In this paper, we present a technique, called the logarithmic calendar queue (LCQ), that can achieve a dramatic reduction of the implementation complexity of a GPS-related scheduler, at the cost of a very small and controllable degradation of the delay bounds. We then use the LCQ to implement MD-SCFQ with reduced complexity. By applying the general methodology for the delay analysis presented in the first part of this paper (Chiussi et al. 1997), we are able to provide a closed-form expression of the delay bounds as a function of the LCQ design parameters, which can be used to optimize the design. The LCQ is not exclusively related to MD-SCFQ, but can be applied to any GPS-related scheduler to simplify implementation complexity.

The speedup of a switch is the factor by which the switch, and hence the memory used in the switch, runs faster compared to the line rate. In high-speed switches, line rates are already touching the limits at which memory can operate. It is very important for a switch to run at as low a speedup as possible. For an input queued (IQ) switch at speedup 1, 100% throughput can be achieved for any admissible traffic (McKeown, N. et al., 1999; Dai, J. and Prabhakar, B., 2000). This gives finite average delays but does not guarantee control on packet delays. S.T. Chuang et al. (see IEEE J. Selected Areas of Commun., vol.17, no.6, p.1030-9, 1999) show that a combined input output queued (CIOQ) switch can emulate perfectly an output queued (OQ) switch at a speedup of 2 and, thus, control the packet delays. This motivates a study of the possibility of obtaining delay control at speedup less than 2. To guarantee optimal control of delays for a general class of traffic, as shown by Chuang et al., speedup 2 is necessary. Hence, to obtain control of delays at lower speedup, we need to restrict the class of arrival traffic. We study the speedup requirement for a class of admissible traffic, which we denote as (1, nF)-regulated traffic, with parameters n and F. We obtain the necessary speedup for this class of traffic. Further, we present a general class of algorithms working at the necessary speedups and thus providing bounded delays.